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Searched refs:SOCFPGA_SDR_ADDRESS (Results 1 – 8 of 8) sorted by relevance

/u-boot/drivers/ddr/altera/
A Dsequencer.h85 #define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0)
86 #define SDR_PHYGRP_PHYMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x1000)
87 #define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000)
88 #define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000)
89 #define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800)
A Dsdram_arria10.c52 (void *)SOCFPGA_SDR_ADDRESS;
A Dsequencer.c3909 if (sdr != (struct socfpga_sdr *)SOCFPGA_SDR_ADDRESS) in sdram_calibration_full()
/u-boot/arch/arm/mach-socfpga/include/mach/
A Dbase_addr_s10.h12 #define SOCFPGA_SDR_ADDRESS 0xf8011000 macro
A Dbase_addr_a10.h42 #define SOCFPGA_SDR_ADDRESS 0xffcfb000 macro
A Dbase_addr_ac5.h30 #define SOCFPGA_SDR_ADDRESS 0xffc20000 macro
A Dsdram_gen5.h18 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
/u-boot/drivers/fpga/
A Dsocfpga_gen5.c219 writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS); in socfpga_load()

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