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Searched refs:SUNXI_DRAM_COM_BASE (Results 1 – 12 of 12) sorted by relevance

/u-boot/arch/arm/include/asm/arch-sunxi/
A Dcpu_sun50i_h6.h32 #define SUNXI_DRAM_COM_BASE 0x04002000 macro
41 #define SUNXI_DRAM_COM_BASE 0x047FA000 macro
A Ddram_sun8i_a83t.h173 #define MCTL_PROTECT (SUNXI_DRAM_COM_BASE + 0x800)
174 #define MCTL_MASTER_CFG0(x) (SUNXI_DRAM_COM_BASE + 0x10 + 0x8 * x)
175 #define MCTL_MASTER_CFG1(x) (SUNXI_DRAM_COM_BASE + 0x14 + 0x8 * x)
A Dcpu_sun9i.h44 #define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000) macro
A Dcpu_sun4i.h155 #define SUNXI_DRAM_COM_BASE 0x01c62000 macro
/u-boot/arch/arm/mach-sunxi/
A Ddram_sunxi_dw.c95 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
117 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()
142 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_v3s()
165 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_a64()
192 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h5()
220 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_r40()
390 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_cr()
475 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_channel_init()
768 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
A Ddram_sun8i_a33.c37 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_cr()
208 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_channel_init()
303 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_sys_init()
332 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
A Ddram_sun50i_h6.c106 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
128 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority()
158 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_sys_init()
288 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_com_init()
417 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_channel_init()
667 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
A Ddram_sun6i.c107 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_channel_init()
267 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_com_init()
298 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_port_cfg()
333 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
A Ddram_sun8i_a83t.c36 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_cr()
264 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_channel_init()
430 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
A Ddram_sun9i.c205 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_sys_init()
343 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_com_init()
828 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in DRAMC_get_dram_size()
859 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
A Ddram_sun50i_h616.c44 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()
66 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority()
99 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_sys_init()
677 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_phy_init()
841 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_ctrl_init()
A Ddram_sun8i_a23.c97 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_init()
271 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()

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