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Searched refs:SUNXI_DRAM_CTL0_BASE (Results 1 – 19 of 19) sorted by relevance

/u-boot/arch/arm/include/asm/arch-sunxi/
A Ddram_sun8i_a83t.h150 #define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x)
151 #define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x)
152 #define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x)
154 #define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x)
155 #define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x)
156 #define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x)
157 #define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x)
158 #define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x)
162 #define DXMDLR0 (SUNXI_DRAM_CTL0_BASE + 0x00000300)
170 #define MX_UPD0 (SUNXI_DRAM_CTL0_BASE + 0x00000880)
[all …]
A Ddram_sun8i_a33.h149 #define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x)
150 #define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x)
151 #define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x)
152 #define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x)
153 #define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x)
A Dcpu_sun50i_h6.h33 #define SUNXI_DRAM_CTL0_BASE 0x04003000 macro
42 #define SUNXI_DRAM_CTL0_BASE 0x047FB000 macro
A Dcpu_sun9i.h45 #define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000) macro
A Dcpu_sun4i.h156 #define SUNXI_DRAM_CTL0_BASE 0x01c63000 macro
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun8i_a33.c91 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in auto_set_timing_para()
175 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_pir()
184 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_data_train_cfg()
195 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_train_dram()
206 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
301 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_sys_init()
334 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in sunxi_dram_init()
A Ddram_sun8i_a83t.c90 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in auto_set_timing_para()
207 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_pir()
216 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_data_train_cfg()
227 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_train_dram()
262 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
395 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_sys_init()
432 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in sunxi_dram_init()
A Ddram_sunxi_dw.c24 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_phy_init()
33 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_bit_delays()
301 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_h3_zq_calibration_quirk()
368 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_v3s_zq_calibration_quirk()
422 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_sys_init()
477 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
770 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in sunxi_dram_init()
A Ddram_sun50i_h6.c160 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_sys_init()
202 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_addrmap()
290 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_com_init()
419 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
A Ddram_sun50i_h616.c101 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_sys_init()
146 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_addrmap()
679 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_phy_init()
843 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_ctrl_init()
A Ddram_sun9i.c287 mctl_ctl_sched_init(SUNXI_DRAM_CTL0_BASE); in mctl_sys_init()
454 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
A Ddram_sun8i_a23.c99 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_init()
A Ddram_sun6i.c112 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
/u-boot/arch/arm/mach-sunxi/dram_timings/
A Dh616_ddr3_1333.c21 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_timing_params()
A Dddr2_v3s.c8 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_timing_params()
A Dddr3_1333.c8 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_timing_params()
A Dlpddr3_stock.c8 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_timing_params()
A Dh6_lpddr3.c23 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_timing_params()
A Dh6_ddr3_1333.c44 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_set_timing_params()

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