SYSCTL_CLKCFG0_REG (reference) in projects: u-boot

Searched refs:SYSCTL_CLKCFG0_REG (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/mips/mach-mtmips/mt7628/
A D	mt7628.h	`44 #define SYSCTL_CLKCFG0_REG 0x2c macro`
A D	init.c	`36 val = readl(sysc + SYSCTL_CLKCFG0_REG); in set_init_timer_freq()`
A D	ddr.c	`140 lspd = readl(sysc + SYSCTL_CLKCFG0_REG) & in mt7628_ddr_init()`
A D	lowlevel_init.S	`35 li t2, KSEG1ADDR(SYSCTL_BASE + SYSCTL_CLKCFG0_REG)`
/u-boot/arch/mips/mach-mtmips/mt7620/
A D	mt7620.h	`57 #define SYSCTL_CLKCFG0_REG 0x2c macro`
A D	sysc.c	`73 val = readl(priv->base + SYSCTL_CLKCFG0_REG); in mt7620_sysc_ioctl()`

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