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Searched refs:SYSCTL_SYSCFG0_REG (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/mips/mach-mtmips/mt7628/
A Dinit.c27 bs = readl(sysc + SYSCTL_SYSCFG0_REG); in set_init_timer_freq()
64 val = readl(sysc + SYSCTL_SYSCFG0_REG); in print_cpuinfo()
A Dmt7628.h32 #define SYSCTL_SYSCFG0_REG 0x10 macro
A Dddr.c138 ddr_type = readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE; in mt7628_ddr_init()
/u-boot/arch/mips/mach-mtmips/mt7620/
A Dinit.c92 val = readl(sysc + SYSCTL_SYSCFG0_REG); in mt7620_get_clks()
158 val = readl(sysc + SYSCTL_SYSCFG0_REG); in print_cpuinfo()
A Dmt7620.h31 #define SYSCTL_SYSCFG0_REG 0x10 macro
A Ddram.c75 ddr_type = (readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE_M) in mt7620_dram_init()

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