| /u-boot/drivers/mtd/nand/raw/ |
| A D | nand_ids.c | 28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
48 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
51 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
54 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
57 SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
66 SZ_8K, SZ_4K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
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| A D | cortina_nand.c | 327 (SZ_4K - 1) << 8); in ca_nand_command()
530 } else if (mtd->writesize == SZ_4K) { in set_bus_width_page_size()
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| /u-boot/arch/arm/mach-stm32mp/ |
| A D | dram_init.c | 51 reg = lmb_alloc(&lmb, CONFIG_SYS_MALLOC_LEN + total_size, SZ_4K); in board_get_usable_ram_top()
54 return ALIGN(reg + CONFIG_SYS_MALLOC_LEN + total_size, SZ_4K); in board_get_usable_ram_top()
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| /u-boot/include/configs/ |
| A D | at91rm9200ek.h | 157 SZ_4K)
159 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
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| A D | devkit3250.h | 30 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
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| A D | smartweb.h | 169 #define CONFIG_SPL_MAX_SIZE (SZ_4K)
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| /u-boot/include/linux/ |
| A D | sizes.h | 26 #define SZ_4K 0x00001000 macro
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| /u-boot/arch/arm/mach-socfpga/include/mach/ |
| A D | secure_vab.h | 19 #define MAX_CERT_SIZE (SZ_4K)
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| /u-boot/arch/arm/include/asm/arch-imx8/ |
| A D | image.h | 18 #define CONTAINER_HDR_QSPI_OFFSET SZ_4K
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| /u-boot/drivers/pci/ |
| A D | pcie_layerscape.h | 98 #define PCIE_BAR0_SIZE SZ_4K
100 #define PCIE_BAR2_SIZE SZ_4K
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| A D | pcie_layerscape_gen4.c | 494 if (cfg_size < SZ_4K) { in ls_pcie_g4_probe()
496 PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_4K); in ls_pcie_g4_probe()
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| A D | pcie_layerscape_ep.c | 130 if (size < SZ_4K) in ls_pcie_ep_setup_bar()
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| /u-boot/arch/arm/mach-uniphier/dram/ |
| A D | cmd_ddrmphy.c | 77 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
101 phy_base = ioremap(param->phy[phy].base, SZ_4K); in zq_dump()
248 phy_base = ioremap(param->phy[phy].base, SZ_4K); in reg_dump()
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| A D | cmd_ddrphy.c | 92 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
224 phy_base = ioremap(param->phy[phy].base, SZ_4K); in reg_dump()
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| /u-boot/fs/btrfs/ |
| A D | disk-io.h | 11 #define BTRFS_SUPER_INFO_SIZE SZ_4K
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| /u-boot/arch/x86/cpu/slimbootloader/ |
| A D | sdram.c | 82 addr_end = rounddown(addr_end - total_size, SZ_4K); in board_get_usable_ram_top()
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| /u-boot/drivers/reset/ |
| A D | reset-uniphier.c | 254 priv->base = devm_ioremap(dev, addr, SZ_4K); in uniphier_reset_probe()
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| /u-boot/drivers/clk/uniphier/ |
| A D | clk-uniphier-core.c | 260 priv->base = devm_ioremap(dev, addr, SZ_4K); in uniphier_clk_probe()
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| /u-boot/drivers/pinctrl/uniphier/ |
| A D | pinctrl-uniphier-core.c | 429 priv->base = devm_ioremap(dev, addr, SZ_4K); in uniphier_pinctrl_probe()
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| /u-boot/arch/arm/include/asm/arch-mx7ulp/ |
| A D | imx-regs.h | 35 #define AIPS1_SLOT_SIZE (SZ_4K)
37 #define AIPS0_SLOT_SIZE (SZ_4K)
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| /u-boot/drivers/smem/ |
| A D | msm_smem.c | 635 ptable = smem->regions[0].virt_base + smem->regions[0].size - SZ_4K; in qcom_smem_get_ptable()
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| /u-boot/common/ |
| A D | bootm.c | 41 #define MAX_CMDLINE_SIZE SZ_4K
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| /u-boot/drivers/mtd/ |
| A D | mtdpart.c | 112 if (partition->size < SZ_4K) { in mtd_parse_partition()
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| /u-boot/drivers/mtd/spi/ |
| A D | spi-nor-core.c | 1943 if (erasesize == SZ_4K) { in spi_nor_parse_bfpt()
|