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Searched refs:TIMING_CFG_2_CPO_MASK (Results 1 – 2 of 2) sorted by relevance

/u-boot/include/
A Dfsl_ddr_sdram.h134 #define TIMING_CFG_2_CPO_MASK 0x0F800000 macro
/u-boot/drivers/ddr/fsl/
A Dmpc85xx_ddr_gen3.c513 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); in fsl_ddr_set_memctl_regs()

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