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/u-boot/drivers/pinctrl/renesas/
A Dpfc-r7s72100.c17 #define P(bank) (0x0000 + (bank) * 4) argument
18 #define PSR(bank) (0x0100 + (bank) * 4) argument
19 #define PPR(bank) (0x0200 + (bank) * 4) argument
20 #define PM(bank) (0x0300 + (bank) * 4) argument
21 #define PMC(bank) (0x0400 + (bank) * 4) argument
22 #define PFC(bank) (0x0500 + (bank) * 4) argument
23 #define PFCE(bank) (0x0600 + (bank) * 4) argument
24 #define PNOT(bank) (0x0700 + (bank) * 4) argument
25 #define PMSR(bank) (0x0800 + (bank) * 4) argument
28 #define PIBC(bank) (0x4000 + (bank) * 4) argument
[all …]
A Dsh_pfc.h415 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
542 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
543 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
544 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
545 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
546 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
547 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
548 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
549 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
557 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
[all …]
/u-boot/drivers/gpio/
A Dgpio-rza1.c15 #define P(bank) (0x0000 + (bank) * 4) argument
16 #define PSR(bank) (0x0100 + (bank) * 4) argument
17 #define PPR(bank) (0x0200 + (bank) * 4) argument
18 #define PM(bank) (0x0300 + (bank) * 4) argument
19 #define PMC(bank) (0x0400 + (bank) * 4) argument
20 #define PFC(bank) (0x0500 + (bank) * 4) argument
21 #define PFCE(bank) (0x0600 + (bank) * 4) argument
22 #define PNOT(bank) (0x0700 + (bank) * 4) argument
23 #define PMSR(bank) (0x0800 + (bank) * 4) argument
26 #define PIBC(bank) (0x4000 + (bank) * 4) argument
[all …]
A Domap_gpio.c54 void *reg = bank->base; in _set_gpio_direction()
73 void *reg = bank->base; in _get_gpio_direction()
89 void *reg = bank->base; in _set_gpio_dataout()
103 void *reg = bank->base; in _get_gpio_value()
146 const struct gpio_bank *bank; in gpio_set_value() local
150 bank = get_gpio_bank(gpio); in gpio_set_value()
161 const struct gpio_bank *bank; in gpio_get_value() local
165 bank = get_gpio_bank(gpio); in gpio_get_value()
175 const struct gpio_bank *bank; in gpio_direction_input() local
180 bank = get_gpio_bank(gpio); in gpio_direction_input()
[all …]
A Dintel_ich6_gpio.c64 if (bank->use_lvl_write_cache) in _ich6_gpio_set_value()
65 val = bank->lvl_write_cache; in _ich6_gpio_set_value()
67 val = inl(bank->lvl); in _ich6_gpio_set_value()
73 outl(val, bank->lvl); in _ich6_gpio_set_value()
74 if (bank->use_lvl_write_cache) in _ich6_gpio_set_value()
75 bank->lvl_write_cache = val; in _ich6_gpio_set_value()
140 bank->lvl_write_cache = 0; in ich6_gpio_probe()
156 tmplong = inl(bank->use_sel); in ich6_gpio_request()
192 tmplong = inl(bank->lvl); in ich6_gpio_get_value()
193 if (bank->use_lvl_write_cache) in ich6_gpio_get_value()
[all …]
A Ds5p_gpio.c39 struct s5p_gpio_bank *bank; member
45 struct s5p_gpio_bank *bank; member
65 return bank; in s5p_gpio_get_bank()
79 value = readl(&bank->con); in s5p_gpio_cfg_pin()
82 writel(value, &bank->con); in s5p_gpio_cfg_pin()
89 value = readl(&bank->dat); in s5p_gpio_set_value()
93 writel(value, &bank->dat); in s5p_gpio_set_value()
110 value = readl(&bank->con); in s5p_gpio_get_cfg_pin()
119 value = readl(&bank->dat); in s5p_gpio_get_value()
297 priv->bank = plat->bank; in gpio_exynos_probe()
[all …]
A Dxilinx_gpio.c40 u32 bank, max_pins; in xilinx_gpio_get_bank_pin() local
44 for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++) { in xilinx_gpio_get_bank_pin()
48 bank, pin_num); in xilinx_gpio_get_bank_pin()
49 *bank_num = bank; in xilinx_gpio_get_bank_pin()
65 u32 bank, pin; in xilinx_gpio_set_value() local
93 u32 bank, pin; in xilinx_gpio_get_value() local
119 u32 bank, pin; in xilinx_gpio_get_function() local
126 if (plat->bank_input[bank]) in xilinx_gpio_get_function()
148 u32 bank, pin; in xilinx_gpio_direction_output() local
155 if (plat->bank_input[bank]) in xilinx_gpio_direction_output()
[all …]
A Dkona_gpio.c21 #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) argument
22 #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) argument
23 #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) argument
24 #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) argument
25 #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) argument
26 #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) argument
27 #define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) argument
28 #define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2)) argument
29 #define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) argument
A Dhi6220_gpio.c16 struct gpio_bank *bank = dev_get_priv(dev); in hi6220_gpio_direction_input() local
19 data = readb(bank->base + HI6220_GPIO_DIR); in hi6220_gpio_direction_input()
21 writeb(data, bank->base + HI6220_GPIO_DIR); in hi6220_gpio_direction_input()
29 struct gpio_bank *bank = dev_get_priv(dev); in hi6220_gpio_set_value() local
38 struct gpio_bank *bank = dev_get_priv(dev); in hi6220_gpio_direction_output() local
41 data = readb(bank->base + HI6220_GPIO_DIR); in hi6220_gpio_direction_output()
43 writeb(data, bank->base + HI6220_GPIO_DIR); in hi6220_gpio_direction_output()
52 struct gpio_bank *bank = dev_get_priv(dev); in hi6220_gpio_get_value() local
54 return !!readb(bank->base + (BIT(gpio + 2))); in hi6220_gpio_get_value()
68 struct gpio_bank *bank = dev_get_priv(dev); in hi6220_gpio_probe() local
[all …]
A Dmxs_gpio.c61 uint32_t bank = PAD_BANK(gpio); in gpio_get_value() local
71 uint32_t bank = PAD_BANK(gpio); in gpio_set_value() local
84 uint32_t bank = PAD_BANK(gpio); in gpio_direction_input() local
96 uint32_t bank = PAD_BANK(gpio); in gpio_direction_output() local
123 unsigned bank, pin; in name_to_gpio() local
129 return bank; in name_to_gpio()
158 unsigned int bank; member
163 unsigned int bank; member
171 PINCTRL_DIN(priv->bank)); in mxs_gpio_get_value()
196 PINCTRL_DOE(priv->bank)); in mxs_gpio_direction_input()
[all …]
/u-boot/cmd/
A Dflash.c62 bank < 1 || bank > CONFIG_SYS_MAX_FLASH_BANKS || in abbrev_spec()
102 for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS && !found; ++bank) { in flash_sect_roundb()
200 for (bank=0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank) { in flash_fill_sect_ranges()
248 if (s_last[bank] < s_first[bank]) { in flash_fill_sect_ranges()
256 (*s_count) += s_last[bank] - s_first[bank] + 1; in flash_fill_sect_ranges()
282 for (bank=0; bank <CONFIG_SYS_MAX_FLASH_BANKS; ++bank) { in do_flinfo()
320 for (bank=1; bank<=CONFIG_SYS_MAX_FLASH_BANKS; ++bank) { in do_flerase()
414 erased += s_last[bank] - s_first[bank] + 1; in flash_sect_erase()
469 for (bank=1; bank<=CONFIG_SYS_MAX_FLASH_BANKS; ++bank) { in do_protect()
614 if (s_first[bank]>=0 && s_first[bank]<=s_last[bank]) { in flash_sect_protect()
[all …]
/u-boot/arch/powerpc/cpu/mpc85xx/
A Dfsl_corenet_serdes.c66 int bank; member
114 int bank = lanes[lane].bank; in serdes_lane_enabled() local
456 clrbits_be32(&regs->bank[bank].pllcr1, in p4080_erratum_serdes_a005()
476 rstctl = in_be32(&srds_regs->bank[bank].rstctl); in wait_for_rstdone()
556 for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) { in fsl_serdes_init()
638 for (bank = 0; bank < SRDS_MAX_BANK; bank++) { in fsl_serdes_init()
648 setbits_be32(&srds_regs->bank[bank].rstctl, in fsl_serdes_init()
651 setbits_be32(&srds_regs->bank[bank].rstctl, in fsl_serdes_init()
668 for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) { in fsl_serdes_init()
673 if (lanes[lane].bank == bank) in fsl_serdes_init()
[all …]
/u-boot/drivers/pinctrl/rockchip/
A Dpinctrl-rockchip-core.c28 if (bank >= ctrl->nr_banks) { in rockchip_verify_config()
52 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
143 if (bank->recalced_mask & BIT(pin)) in rockchip_get_mux()
427 bank = cells[4 * i + 0];
491 struct rockchip_pin_bank *bank; local
498 bank = ctrl->pin_banks;
503 bank->priv = priv;
504 bank->pin_base = ctrl->nr_pins;
505 ctrl->nr_pins += bank->nr_pins;
513 if (bank_pins >= bank->nr_pins)
[all …]
A Dpinctrl-rk3288.c35 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3288_set_mux()
46 mux_type = bank->iomux[iomux_num].type; in rk3288_set_mux()
47 reg = bank->iomux[iomux_num].offset; in rk3288_set_mux()
50 if (bank->route_mask & BIT(pin)) { in rk3288_set_mux()
60 if (bank->bank_num == 0) { in rk3288_set_mux()
84 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
114 type = bank->pull_type[pin_num / 8]; in rk3288_set_pull()
122 if (bank->bank_num == 0) { in rk3288_set_pull()
146 if (bank->bank_num == 0) { in rk3288_calc_drv_reg_and_bit()
170 int type = bank->drv[pin_num / 8].drv_type; in rk3288_set_drive()
[all …]
A Dpinctrl-rv1108.c82 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1108_set_mux()
93 mux_type = bank->iomux[iomux_num].type; in rv1108_set_mux()
94 reg = bank->iomux[iomux_num].offset; in rv1108_set_mux()
97 if (bank->recalced_mask & BIT(pin)) in rv1108_set_mux()
114 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1108_calc_pull_reg_and_bit()
117 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
145 type = bank->pull_type[pin_num / 8]; in rv1108_set_pull()
168 struct rockchip_pinctrl_priv *priv = bank->priv; in rv1108_calc_drv_reg_and_bit()
171 if (bank->bank_num == 0) { in rv1108_calc_drv_reg_and_bit()
195 int type = bank->drv[pin_num / 8].drv_type; in rv1108_set_drive()
[all …]
A Dpinctrl-rk3368.c17 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3368_set_mux()
28 mux_type = bank->iomux[iomux_num].type; in rk3368_set_mux()
29 reg = bank->iomux[iomux_num].offset; in rk3368_set_mux()
46 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3368_calc_pull_reg_and_bit()
49 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
58 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; in rk3368_calc_pull_reg_and_bit()
79 type = bank->pull_type[pin_num / 8]; in rk3368_set_pull()
101 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3368_calc_drv_reg_and_bit()
104 if (bank->bank_num == 0) { in rk3368_calc_drv_reg_and_bit()
113 *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; in rk3368_calc_drv_reg_and_bit()
[all …]
A Dpinctrl-rk3399.c57 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3399_set_mux()
68 mux_type = bank->iomux[iomux_num].type; in rk3399_set_mux()
69 reg = bank->iomux[iomux_num].offset; in rk3399_set_mux()
72 if (bank->route_mask & BIT(pin)) { in rk3399_set_mux()
95 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3399_calc_pull_reg_and_bit()
98 if (bank->bank_num == 0 || bank->bank_num == 1) { in rk3399_calc_pull_reg_and_bit()
130 type = bank->pull_type[pin_num / 8]; in rk3399_set_pull()
149 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3399_calc_drv_reg_and_bit()
153 if (bank->bank_num == 0 || bank->bank_num == 1) in rk3399_calc_drv_reg_and_bit()
158 *reg = bank->drv[drv_num].offset; in rk3399_calc_drv_reg_and_bit()
[all …]
A Dpinctrl-rk3328.c128 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3328_set_mux()
139 mux_type = bank->iomux[iomux_num].type; in rk3328_set_mux()
140 reg = bank->iomux[iomux_num].offset; in rk3328_set_mux()
143 if (bank->recalced_mask & BIT(pin)) in rk3328_set_mux()
146 if (bank->route_mask & BIT(pin)) { in rk3328_set_mux()
168 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3328_calc_pull_reg_and_bit()
191 type = bank->pull_type[pin_num / 8]; in rk3328_set_pull()
212 struct rockchip_pinctrl_priv *priv = bank->priv; in rk3328_calc_drv_reg_and_bit()
216 *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; in rk3328_calc_drv_reg_and_bit()
230 int type = bank->drv[pin_num / 8].drv_type; in rk3328_set_drive()
[all …]
A Dpinctrl-px30.c78 struct rockchip_pinctrl_priv *priv = bank->priv; in px30_set_mux()
89 mux_type = bank->iomux[iomux_num].type; in px30_set_mux()
90 reg = bank->iomux[iomux_num].offset; in px30_set_mux()
93 if (bank->route_mask & BIT(pin)) { in px30_set_mux()
119 struct rockchip_pinctrl_priv *priv = bank->priv; in px30_calc_pull_reg_and_bit()
122 if (bank->bank_num == 0) { in px30_calc_pull_reg_and_bit()
131 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; in px30_calc_pull_reg_and_bit()
151 type = bank->pull_type[pin_num / 8]; in px30_set_pull()
179 if (bank->bank_num == 0) { in px30_calc_drv_reg_and_bit()
188 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; in px30_calc_drv_reg_and_bit()
[all …]
/u-boot/arch/arm/lib/
A Dbootm-fdt.c40 int bank; in arch_fixup_fdt() local
44 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { in arch_fixup_fdt()
45 start[bank] = bd->bi_dram[bank].start; in arch_fixup_fdt()
46 size[bank] = bd->bi_dram[bank].size; in arch_fixup_fdt()
48 ret = armv7_apply_memory_carveout(&start[bank], &size[bank]); in arch_fixup_fdt()
/u-boot/drivers/misc/
A Dmxc_ocotp.c152 if (bank == 8) in fuse_word_physical()
187 if (bank >= FUSE_BANKS || in prepare_access()
195 if ((bank == 7 || bank == 8) && in prepare_access()
246 phy_bank = fuse_bank_physical(bank); in fuse_read()
314 u32 addr = bank; in setup_direct_access()
316 u32 addr = bank << 2 | word; in setup_direct_access()
321 bank = bank - 1; in setup_direct_access()
324 addr = bank << 3 | word; in setup_direct_access()
375 if (bank != 0 && bank != 1) { in prepare_write()
378 bank != 9 && bank != 10 && bank != 28)) { in prepare_write()
[all …]
A Dfsl_iim.c94 } bank[8]; member
106 if (bank >= ARRAY_SIZE((*regs)->bank) || in prepare_access()
107 word >= ARRAY_SIZE((*regs)->bank[0].word) || in prepare_access()
143 int fuse_read(u32 bank, u32 word, u32 *val) in fuse_read() argument
153 *val = iim_read32(&regs->bank[bank].word[word]); in fuse_read()
167 iim_write32(&regs->ua, bank << 3 | word >> 5); in direct_access()
177 int fuse_sense(u32 bank, u32 word, u32 *val) in fuse_sense() argument
235 int fuse_prog(u32 bank, u32 word, u32 val) in fuse_prog() argument
248 ret = prog_bit(regs, bank, word, bit); in fuse_prog()
259 int fuse_override(u32 bank, u32 word, u32 val) in fuse_override() argument
[all …]
/u-boot/drivers/pinctrl/
A Dpinctrl-sti.c50 unsigned char bank; member
64 int bank = pin_desc->bank; in sti_alternate_select() local
69 switch (bank) { in sti_alternate_select()
71 sysconfreg += bank; in sti_alternate_select()
74 sysconfreg += bank - 10; in sti_alternate_select()
77 sysconfreg += bank - 30; in sti_alternate_select()
99 int bank = pin_desc->bank; in sti_pin_configure() local
153 switch (bank) { in sti_pin_configure()
158 bank -= 10; in sti_pin_configure()
162 bank -= 30; in sti_pin_configure()
[all …]
/u-boot/drivers/reset/
A Dstm32-reset.c43 int bank = (reset_ctl->id / BITS_PER_LONG) * 4; in stm32_reset_assert() local
47 reset_ctl->id, bank, offset); in stm32_reset_assert()
50 if (bank != RCC_MP_GCR_OFFSET) in stm32_reset_assert()
52 writel(BIT(offset), priv->base + bank); in stm32_reset_assert()
54 clrbits_le32(priv->base + bank, BIT(offset)); in stm32_reset_assert()
56 setbits_le32(priv->base + bank, BIT(offset)); in stm32_reset_assert()
64 int bank = (reset_ctl->id / BITS_PER_LONG) * 4; in stm32_reset_deassert() local
68 reset_ctl->id, bank, offset); in stm32_reset_deassert()
71 if (bank != RCC_MP_GCR_OFFSET) in stm32_reset_deassert()
75 setbits_le32(priv->base + bank, BIT(offset)); in stm32_reset_deassert()
[all …]
/u-boot/arch/arm/mach-tegra/
A Dcboot.c248 memmove(&tegra_mem_map[bank + 1], &tegra_mem_map[bank], in mark_ram_allocated()
249 CONFIG_NR_DRAM_BANKS - bank - 1); in mark_ram_allocated()
251 bank++; in mark_ram_allocated()
267 tegra_mem_map[bank].size = 0; in mark_ram_allocated()
273 int bank; in reserve_ram() local
276 for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) { in reserve_ram()
283 mark_ram_allocated(bank, start, end); in reserve_ram()
290 int bank; in alloc_ram() local
292 for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) { in alloc_ram()
401 int bank; in dump_ram_banks() local
[all …]

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