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Searched refs:bar (Results 1 – 25 of 91) sorted by relevance

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/u-boot/test/dm/
A Dpci.c254 void *bar; in dm_test_pci_ea() local
272 ut_assertnonnull(bar); in dm_test_pci_ea()
273 *(int *)bar = 2; /* swap upper/lower */ in dm_test_pci_ea()
276 ut_assertnonnull(bar); in dm_test_pci_ea()
277 strcpy(bar, "ea TEST"); in dm_test_pci_ea()
278 unmap_sysmem(bar); in dm_test_pci_ea()
280 ut_assertnonnull(bar); in dm_test_pci_ea()
281 ut_asserteq_str("EA test", bar); in dm_test_pci_ea()
285 ut_assertnonnull(bar); in dm_test_pci_ea()
289 ut_assertnull(bar); in dm_test_pci_ea()
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A Dpci_ep.c31 struct pci_bar bar = { in dm_test_pci_ep_base() local
52 ut_assertok(pci_ep_set_bar(bus, 0, &bar)); in dm_test_pci_ep_base()
55 ut_asserteq_mem(&tmp_bar, &bar, sizeof(bar)); in dm_test_pci_ep_base()
/u-boot/drivers/power/acpi_pmc/
A Dpmc_emul.c24 u32 bar[6]; member
82 u32 *bar; in sandbox_pmc_emul_read_config() local
85 bar = &plat->bar[barnum]; in sandbox_pmc_emul_read_config()
87 *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type, in sandbox_pmc_emul_read_config()
111 u32 *bar; in sandbox_pmc_emul_write_config() local
114 bar = &plat->bar[barnum]; in sandbox_pmc_emul_write_config()
117 *bar = value; in sandbox_pmc_emul_write_config()
119 *bar |= barinfo[barnum].type; in sandbox_pmc_emul_write_config()
135 u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE; in sandbox_pmc_emul_find_bar()
/u-boot/doc/uImage.FIT/
A Doverlay-fdt-boot.txt77 foo-reva-bar.dtb {
81 foo-revb-bar.dtb {
89 foo-revb-bar-baz.dtb {
105 foo-reva.dtb, foo-revb.dtb, foo-reva-bar.dtb, foo-revb-bar.dtb,
147 data = /incbin/("./bar.dtbo");
170 foo-reva-bar.dtb {
174 foo-revb-bar.dtb {
182 foo-revb-bar-baz.dtb {
186 bar {
214 # bootm <addr>#foo-reva.dtb#bar
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/u-boot/drivers/pci/
A Dpcie_layerscape_gen4.c313 int bar, u64 phys) in ls_pcie_g4_ep_inbound_win_set() argument
318 if (bar == 1) { in ls_pcie_g4_ep_inbound_win_set()
332 int bar; in ls_pcie_g4_ep_setup_wins() local
339 for (bar = 0; bar < PF_BAR_NUM; bar++) { in ls_pcie_g4_ep_setup_wins()
360 u32 bar_pos = BAR_POS(bar, pf, vf_bar); in ls_pcie_g4_ep_enable_bar()
383 int bar, bool vf_bar, u64 size) in ls_pcie_g4_ep_setup_bar() argument
393 int bar; in ls_pcie_g4_ep_setup_bars() local
396 for (bar = 0; bar < PF_BAR_NUM; bar++) in ls_pcie_g4_ep_setup_bars()
397 ls_pcie_g4_ep_setup_bar(pcie, pf, bar, false, bar_size[bar]); in ls_pcie_g4_ep_setup_bars()
403 for (bar = 0; bar < VF_BAR_NUM; bar++) in ls_pcie_g4_ep_setup_bars()
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A Dpci_auto.c29 int bar, bar_nr = 0; in dm_pciauto_setup_device() local
41 for (bar = PCI_BASE_ADDRESS_0; in dm_pciauto_setup_device()
42 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { in dm_pciauto_setup_device()
46 dm_pci_write_config32(dev, bar, 0xffffffff); in dm_pciauto_setup_device()
47 dm_pci_read_config32(dev, bar, &bar_response); in dm_pciauto_setup_device()
71 dm_pci_read_config32(dev, bar + 4, in dm_pciauto_setup_device()
99 printf("PCI: Failed autoconfig bar %x\n", bar); in dm_pciauto_setup_device()
103 dm_pci_write_config32(dev, bar, (u32)bar_value); in dm_pciauto_setup_device()
106 bar += 4; in dm_pciauto_setup_device()
108 dm_pci_write_config32(dev, bar, in dm_pciauto_setup_device()
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A Dpci_auto_old.c38 int bar, bar_nr = 0; in pciauto_setup_device() local
49 for (bar = PCI_BASE_ADDRESS_0; in pciauto_setup_device()
50 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { in pciauto_setup_device()
52 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); in pciauto_setup_device()
53 pci_hose_read_config_dword(hose, dev, bar, &bar_response); in pciauto_setup_device()
75 pci_hose_write_config_dword(hose, dev, bar + 4, in pciauto_setup_device()
77 pci_hose_read_config_dword(hose, dev, bar + 4, in pciauto_setup_device()
100 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value); in pciauto_setup_device()
103 bar += 4; in pciauto_setup_device()
105 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32)); in pciauto_setup_device()
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A Dpci_common.c104 void *pci_map_bar(pci_dev_t pdev, int bar, int flags) in pci_map_bar() argument
110 pci_read_config_dword(pdev, bar, &bar_response); in pci_map_bar()
125 int bar; in pci_write_bar32() local
127 bar = PCI_BASE_ADDRESS_0 + barnum * 4; in pci_write_bar32()
128 pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl); in pci_write_bar32()
134 int bar; in pci_read_bar32() local
136 bar = PCI_BASE_ADDRESS_0 + barnum * 4; in pci_read_bar32()
137 pci_hose_read_config_dword(hose, dev, bar, &addr); in pci_read_bar32()
A Dpci_ftpci100.c70 devs[priv->ndevs].bar[i].addr = priv->io_base; in setup_pci_bar()
71 devs[priv->ndevs].bar[i].size = size_mask + 1; in setup_pci_bar()
110 devs[priv->ndevs].bar[i].addr = alloc_base; in setup_pci_bar()
111 devs[priv->ndevs].bar[i].size = size_mask + 1; in setup_pci_bar()
115 devs[priv->ndevs].bar[0].addr, in setup_pci_bar()
116 devs[priv->ndevs].bar[0].size); in setup_pci_bar()
215 devs[priv->ndevs].bar[0].addr, in pci_bus_scan()
216 devs[priv->ndevs].bar[0].size, in pci_bus_scan()
A Dpci.c200 int bar, found_mem64; in pci_hose_config_device() local
207 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { in pci_hose_config_device()
208 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); in pci_hose_config_device()
209 pci_hose_read_config_dword(hose, dev, bar, &bar_response); in pci_hose_config_device()
229 pci_hose_write_config_dword(hose, dev, bar + 4, in pci_hose_config_device()
231 pci_hose_read_config_dword(hose, dev, bar + 4, in pci_hose_config_device()
250 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value); in pci_hose_config_device()
253 bar += 4; in pci_hose_config_device()
255 pci_hose_write_config_dword(hose, dev, bar, in pci_hose_config_device()
258 pci_hose_write_config_dword(hose, dev, bar, 0x00000000); in pci_hose_config_device()
A Dpcie_layerscape_gen4.h49 #define BAR_POS(bar, pf, vf_bar) \ argument
50 ((bar) + (pf) * PF_BAR_NUM + (vf_bar) * PCIE_PF_NUM * PF_BAR_NUM)
144 #define PAB_PEX_BAR_AMAP(pf, bar) \ argument
145 (0x1ba0 + 0x20 * (pf) + 4 * (bar))
147 #define PAB_EXT_PEX_BAR_AMAP(pf, bar) \ argument
148 (0x84a0 + 0x20 * (pf) + 4 * (bar))
/u-boot/drivers/misc/
A Dp2sb_emul.c28 u32 bar[6]; member
89 u32 *bar; in sandbox_p2sb_emul_read_config() local
92 bar = &plat->bar[barnum]; in sandbox_p2sb_emul_read_config()
94 *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type, in sandbox_p2sb_emul_read_config()
118 u32 *bar; in sandbox_p2sb_emul_write_config() local
121 bar = &plat->bar[barnum]; in sandbox_p2sb_emul_write_config()
124 *bar = value; in sandbox_p2sb_emul_write_config()
126 *bar |= barinfo[barnum].type; in sandbox_p2sb_emul_write_config()
142 u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE; in sandbox_p2sb_emul_find_bar()
A Dswap_case.c25 u32 bar[6]; member
144 u32 *bar; in sandbox_swap_case_read_config() local
147 bar = &plat->bar[barnum]; in sandbox_swap_case_read_config()
149 *valuep = sandbox_pci_read_bar(*bar, barinfo[barnum].type, in sandbox_swap_case_read_config()
212 u32 *bar; in sandbox_swap_case_write_config() local
215 bar = &plat->bar[barnum]; in sandbox_swap_case_write_config()
218 *bar = value; in sandbox_swap_case_write_config()
220 *bar |= barinfo[barnum].type; in sandbox_swap_case_write_config()
236 u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE; in sandbox_swap_case_find_bar()
/u-boot/arch/powerpc/cpu/mpc83xx/
A Dlaw.c29 ecm->bar = start & 0xfffff000; in set_ddr_laws()
31 debug("DDR:bar=0x%08x\n", ecm->bar); in set_ddr_laws()
46 ecm->bar = start & 0xfffff000; in set_ddr_laws()
48 debug("DDR:bar=0x%08x\n", ecm->bar); in set_ddr_laws()
A Dcpu_init.c211 im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM; in cpu_init_f()
218 im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM; in cpu_init_f()
222 im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM; in cpu_init_f()
226 im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM; in cpu_init_f()
230 im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM; in cpu_init_f()
234 im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM; in cpu_init_f()
238 im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM; in cpu_init_f()
242 im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM; in cpu_init_f()
/u-boot/drivers/pci_endpoint/
A Dpcie-cadence-ep.c56 enum pci_barno bar = ep_bar->barno; in cdns_set_bar() local
77 if (is_64bits && (bar & 1)) in cdns_set_bar()
95 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), in cdns_set_bar()
97 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), in cdns_set_bar()
100 if (bar < BAR_4) { in cdns_set_bar()
102 b = bar; in cdns_set_bar()
105 b = bar - BAR_4; in cdns_set_bar()
A Dpcie-cadence.h165 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ argument
166 (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008)
170 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ argument
171 (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
183 #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ argument
184 (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)
185 #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ argument
186 (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008)
/u-boot/board/freescale/mpc837xerdb/
A Dpci.c80 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; in pci_init_board()
83 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; in pci_init_board()
102 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); in pci_init_board()
105 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); in pci_init_board()
/u-boot/arch/x86/cpu/intel_common/
A Dfast_spi.c50 ulong bar, mmio_base; in fast_spi_get_bios_mmap() local
53 pci_x86_read_config(pdev, PCI_BASE_ADDRESS_0, &bar, PCI_SIZE_32); in fast_spi_get_bios_mmap()
54 mmio_base = bar & PCI_BASE_ADDRESS_MEM_MASK; in fast_spi_get_bios_mmap()
/u-boot/include/
A Dpci_ep.h122 struct pci_bar *bar);
133 struct pci_bar *bar, enum pci_barno barno);
143 enum pci_barno bar);
281 int pci_ep_set_bar(struct udevice *dev, uint func_num, struct pci_bar *bar);
303 int pci_ep_clear_bar(struct udevice *dev, uint func_num, enum pci_barno bar);
/u-boot/arch/x86/cpu/quark/
A Dquark.c302 u32 bar; in quark_usb_init() local
305 qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar); in quark_usb_init()
306 writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01); in quark_usb_init()
309 qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar); in quark_usb_init()
310 writel(0x7f, bar + USBD_INT_MASK); in quark_usb_init()
311 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK); in quark_usb_init()
312 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS); in quark_usb_init()
/u-boot/board/freescale/mpc832xemds/
A Dpci.c73 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; in pci_init_board()
76 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
131 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
134 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
/u-boot/board/freescale/mpc837xemds/
A Dpci.c99 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; in pci_init_board()
102 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; in pci_init_board()
131 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); in pci_init_board()
134 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); in pci_init_board()
/u-boot/api/
A Dapi_platform-powerpc.c39 si->bar = gd->bd->bi_bar; in platform_sys_info()
42 si->bar = 0; in platform_sys_info()
/u-boot/board/sbc8349/
A Dpci.c61 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; in pci_init_board()
64 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()

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