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Searched refs:bus_width (Results 1 – 25 of 84) sorted by relevance

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/u-boot/drivers/mmc/
A Ds5p_sdhci.c99 if (host->bus_width == 8) in s5p_sdhci_core_init()
109 int s5p_sdhci_init(u32 regbase, int index, int bus_width) in s5p_sdhci_init() argument
118 host->bus_width = bus_width; in s5p_sdhci_init()
127 flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; in do_sdhci_init()
158 int bus_width, dev_id; in sdhci_get_config() local
170 bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); in sdhci_get_config()
171 if (bus_width <= 0) { in sdhci_get_config()
175 host->bus_width = bus_width; in sdhci_get_config()
A Drockchip_sdhci.c69 if (host->bus_width == 8) in arasan_sdhci_probe()
91 host->bus_width = dev_read_u32_default(dev, "bus-width", 4); in arasan_sdhci_of_to_plat()
A Dfsl_esdhc_imx.c158 unsigned int bus_width; member
1006 if (mmc->bus_width == 4) in esdhc_set_ios_common()
1249 if (priv->bus_width == 8) in fsl_esdhc_init()
1260 if (priv->bus_width < 8) in fsl_esdhc_init()
1262 if (priv->bus_width < 4) in fsl_esdhc_init()
1435 priv->bus_width = 8; in fsl_esdhc_of_to_plat()
1437 priv->bus_width = 4; in fsl_esdhc_of_to_plat()
1439 priv->bus_width = 1; in fsl_esdhc_of_to_plat()
1519 priv->bus_width = 8; in fsl_esdhc_probe()
1521 priv->bus_width = 4; in fsl_esdhc_probe()
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A Darm_pl180_mmci.c320 if (dev->bus_width) { in host_set_ios()
323 switch (dev->bus_width) { in host_set_ios()
334 printf("Invalid bus width: %d\n", dev->bus_width); in host_set_ios()
427 u32 bus_width; in arm_pl180_mmc_probe() local
465 bus_width = dev_read_u32_default(dev, "bus-width", 1); in arm_pl180_mmc_probe()
466 switch (bus_width) { in arm_pl180_mmc_probe()
476 dev_err(dev, "Invalid bus-width value %u\n", bus_width); in arm_pl180_mmc_probe()
A Dsunxi_mmc.c266 mmc->bus_width, mmc->clock); in sunxi_mmc_set_ios_common()
275 if (mmc->bus_width == 8) in sunxi_mmc_set_ios_common()
277 else if (mmc->bus_width == 4) in sunxi_mmc_set_ios_common()
620 int bus_width, ret; in sunxi_mmc_probe() local
623 bus_width = dev_read_u32_default(dev, "bus-width", 1); in sunxi_mmc_probe()
627 if (bus_width == 8) in sunxi_mmc_probe()
629 if (bus_width >= 4) in sunxi_mmc_probe()
A Dtegra_mmc.c445 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); in tegra_mmc_set_ios()
460 if (mmc->bus_width == 8) in tegra_mmc_set_ios()
462 else if (mmc->bus_width == 4) in tegra_mmc_set_ios()
686 int bus_width, ret; in tegra_mmc_probe() local
690 bus_width = dev_read_u32_default(dev, "bus-width", 1); in tegra_mmc_probe()
694 if (bus_width == 8) in tegra_mmc_probe()
696 if (bus_width >= 4) in tegra_mmc_probe()
A Dsh_mmcif.c369 switch (host->bus_width) { in sh_mmcif_set_cmd()
554 if (mmc->bus_width == 8) in sh_mmcif_set_ios_common()
555 host->bus_width = MMC_BUS_WIDTH_8; in sh_mmcif_set_ios_common()
556 else if (mmc->bus_width == 4) in sh_mmcif_set_ios_common()
557 host->bus_width = MMC_BUS_WIDTH_4; in sh_mmcif_set_ios_common()
559 host->bus_width = MMC_BUS_WIDTH_1; in sh_mmcif_set_ios_common()
561 debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width); in sh_mmcif_set_ios_common()
/u-boot/drivers/ddr/marvell/a38x/
A Dmv_ddr_topology.c75 iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data); in mv_ddr_topology_map_update()
131 iface_params->bus_width = MV_DDR_DEV_WIDTH_8BIT; in mv_ddr_topology_map_update()
182 unsigned int bus_width; in mv_ddr_if_bus_width_get() local
188 bus_width = 16; in mv_ddr_if_bus_width_get()
193 bus_width = 32; in mv_ddr_if_bus_width_get()
197 bus_width = 64; in mv_ddr_if_bus_width_get()
201 bus_width = 0; in mv_ddr_if_bus_width_get()
204 return bus_width; in mv_ddr_if_bus_width_get()
276 if (iface_params->bus_width == MV_DDR_DEV_WIDTH_8BIT) in mv_ddr_mem_sz_per_cs_get()
278 else if (iface_params->bus_width == MV_DDR_DEV_WIDTH_16BIT) in mv_ddr_mem_sz_per_cs_get()
A Dmv_ddr_training_db.h35 u32 mv_ddr_page_size_get(enum mv_ddr_dev_width bus_width, enum mv_ddr_die_capacity mem_size);
/u-boot/arch/arm/mach-s5pc1xx/include/mach/
A Dmmc.h55 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
57 static inline int s5p_mmc_init(int index, int bus_width) in s5p_mmc_init() argument
62 return s5p_sdhci_init(base, index, bus_width); in s5p_mmc_init()
/u-boot/arch/arm/mach-exynos/include/mach/
A Dmmc.h57 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
59 static inline int s5p_mmc_init(int index, int bus_width) in s5p_mmc_init() argument
64 return s5p_sdhci_init(base, index, bus_width); in s5p_mmc_init()
/u-boot/drivers/ddr/fsl/
A Dddr3_dimm_params.c64 if ((spd->bus_width & 0x7) < 4) in compute_ranksize()
65 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; in compute_ranksize()
123 pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); in ddr_compute_dimm_parameters()
124 if ((spd->bus_width >> 3) & 0x3) in ddr_compute_dimm_parameters()
A Dddr4_dimm_params.c100 if ((spd->bus_width & 0x7) < 4) in compute_ranksize()
101 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; in compute_ranksize()
176 pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); in ddr_compute_dimm_parameters()
177 if ((spd->bus_width >> 3) & 0x3) in ddr_compute_dimm_parameters()
A Darm_ddr_gen3.c35 unsigned int i, bus_width; in fsl_ddr_set_memctl_regs() local
224 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) in fsl_ddr_set_memctl_regs()
226 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / in fsl_ddr_set_memctl_regs()
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun6i.c24 u8 bus_width; member
66 if (para->bus_width == 32) { in mctl_dll_init()
76 if (para->bus_width == 32) { in mctl_dll_init()
86 if (para->bus_width == 32) { in mctl_dll_init()
184 para->bus_width = 16; in mctl_channel_init()
245 if (para->bus_width == 16) in mctl_channel_init()
274 ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) | in mctl_com_init()
339 .bus_width = 32, in sunxi_dram_init()
385 bus = (para.bus_width == 32) ? 2 : 1; in sunxi_dram_init()
A Ddram_sun8i_a23.c92 static void mctl_init(u32 *bus_width) in mctl_init() argument
246 *bus_width = 8; in mctl_init()
253 *bus_width = 16; in mctl_init()
273 u32 bus, bus_width, offset, page_size, rows; in sunxi_dram_init() local
276 mctl_init(&bus_width); in sunxi_dram_init()
278 if (bus_width == 16) { in sunxi_dram_init()
A Ddram_sun8i_a33.c30 u8 bus_width; member
42 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | in mctl_set_cr()
235 para->bus_width = 16; in mctl_channel_init()
278 para->bus_width = 8; in mctl_channel_init()
341 .bus_width = 16, in sunxi_dram_init()
361 return para.page_size * (para.bus_width / 8) * in sunxi_dram_init()
A Ddram_sun8i_a83t.c28 u8 bus_width; member
41 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | in mctl_set_cr()
318 para->bus_width = 16; in mctl_channel_init()
370 para->bus_width = 8; in mctl_channel_init()
418 para->bus_width = 16; in mctl_sys_init()
439 .bus_width = 16, in sunxi_dram_init()
471 return para.page_size * (para.bus_width / 8) * in sunxi_dram_init()
/u-boot/arch/arm/include/asm/arch-hi6220/
A Ddwmmc.h7 int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
/u-boot/drivers/video/
A Dmxsfb.c65 uint32_t word_len = 0, bus_width = 0; in mxs_lcd_init() local
101 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT; in mxs_lcd_init()
106 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT; in mxs_lcd_init()
111 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT; in mxs_lcd_init()
116 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT; in mxs_lcd_init()
121 writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE | in mxs_lcd_init()
/u-boot/board/sunxi/
A Ddram_sun4i_auto.c11 .bus_width = 0,
A Ddram_sun5i_auto.c14 .bus_width = 0,
/u-boot/arch/mips/mach-mtmips/include/mach/
A Dddr.h48 u32 bus_width; member
/u-boot/arch/mips/mach-mtmips/mt7628/
A Dddr.c153 param.bus_width = 0; in mt7628_ddr_init()
172 ddr_calibrate(param.memc, param.memsize, param.bus_width); in mt7628_ddr_init()
/u-boot/doc/device-tree-bindings/mmc/
A Dmsm_sdhci.txt13 - bus_width: Width of SD/eMMC bus (default 4)

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