| /u-boot/arch/mips/mach-mtmips/ |
| A D | ddr_init.c | 88 val = cfg->cfg1; in mc_ddr_init()
205 u32 cfg1) in mc_sdr_init() argument
212 writel(cfg1, memc + MEMCTL_SDRAM_CFG1_REG); in mc_sdr_init()
226 u32 cfg1; in sdr_init() local
228 cfg1 = param->sdr_cfg1 | SDRAM_INIT_START; in sdr_init()
229 cfg1 &= ~(NUMCOLS_M | NUMROWS_M); in sdr_init()
233 cfg1 | sdr_size_cfg1[DRAM_64MB]); in sdr_init()
250 cfg1 | sdr_size_cfg1[sz]); in sdr_init()
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| /u-boot/arch/arm/include/asm/mach-imx/ |
| A D | boot_mode.h | 8 #define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \ argument
9 ((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1)
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| /u-boot/drivers/net/ |
| A D | pic32_eth.c | 82 writel(EMAC_SOFTRESET, &emac_p->cfg1.set); /* reset assert */ in pic32_mii_init()
84 writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */ in pic32_mii_init()
179 writel(v, &emac_p->cfg1.raw); in pic32_mac_init()
226 writel(EMAC_SOFTRESET, &emac_p->cfg1.raw); in pic32_mac_reset()
230 writel(0, &emac_p->cfg1.raw); in pic32_mac_reset()
373 writel(EMAC_SOFTRESET, &emac_p->cfg1.raw); in pic32_eth_stop()
376 writel(0, &emac_p->cfg1.raw); in pic32_eth_stop()
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| A D | pic32_eth.h | 42 struct pic32_reg_atomic cfg1; /* 0x200*/ member
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| /u-boot/arch/mips/mach-mtmips/include/mach/ |
| A D | ddr.h | 27 u32 cfg1; member
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| /u-boot/board/freescale/m5208evbe/ |
| A D | m5208evbe.c | 44 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
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| /u-boot/board/freescale/m53017evb/ |
| A D | m53017evb.c | 44 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
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| /u-boot/board/freescale/m5329evb/ |
| A D | m5329evb.c | 41 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
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| /u-boot/board/freescale/m5373evb/ |
| A D | m5373evb.c | 41 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
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| /u-boot/arch/arm/mach-imx/ |
| A D | mmdc_size.c | 22 u32 cfg1; member
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| /u-boot/board/freescale/m547xevb/ |
| A D | m547xevb.c | 58 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
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| /u-boot/board/freescale/m548xevb/ |
| A D | m548xevb.c | 58 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); in dram_init()
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | tve.h | 62 u32 cfg1; /* 0x138 */ member
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| A D | dram_sun50i_h616.h | 48 u32 cfg1; /* 0x4 */ member
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| A D | dram_sun50i_h6.h | 53 u32 cfg1; /* 0x4 */ member
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| /u-boot/board/astro/mcf5373l/ |
| A D | mcf5373l.c | 54 __raw_writel(0x33211530, &sdp->cfg1); in dram_init()
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun50i_h6.c | 114 const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff); in mbus_configure_port() local
116 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1); in mbus_configure_port()
118 writel(cfg1, &mctl_com->master[port].cfg1); in mbus_configure_port()
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| A D | dram_sun50i_h616.c | 52 const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff); in mbus_configure_port() local
54 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1); in mbus_configure_port()
56 writel_relaxed(cfg1, &mctl_com->master[port].cfg1); in mbus_configure_port()
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| A D | dram_sunxi_dw.c | 103 const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff); in mbus_configure_port() local
105 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1); in mbus_configure_port()
107 writel(cfg1, &mctl_com->mcr[port][1]); in mbus_configure_port()
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| /u-boot/drivers/pci/ |
| A D | pcie_layerscape.h | 158 void __iomem *cfg1; member
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| A D | pcie_layerscape_rc.c | 170 *paddress = pcie_rc->cfg1 + offset; in ls_pcie_conf_address()
343 pcie_rc->cfg1 = pcie_rc->cfg0 + in ls_pcie_probe()
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| /u-boot/arch/m68k/include/asm/ |
| A D | immap_520x.h | 168 u32 cfg1; /* 0x08 Cfg 1 */ member
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| A D | immap_547x_8x.h | 70 u32 cfg1; /* 0x08 */ member
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| A D | immap_5301x.h | 288 u32 cfg1; /* 0x08 Cfg 1 */ member
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| /u-boot/arch/powerpc/include/asm/ |
| A D | fsl_liodn.h | 224 offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \
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