Searched refs:clk_src (Results 1 – 14 of 14) sorted by relevance
| /u-boot/include/mvebu/ |
| A D | comphy.h | 15 bool clk_src; member
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| /u-boot/board/freescale/s32v234evb/ |
| A D | clock.c | 19 u32 clk_src; in select_pll_source_clk() local
26 clk_src = SRC_GPR1_FIRC_CLK_SOURCE; in select_pll_source_clk()
29 clk_src = SRC_GPR1_XOSC_CLK_SOURCE; in select_pll_source_clk()
53 writel(readl(&src->gpr1) | SRC_GPR1_PLL_SOURCE(pll_idx, clk_src), in select_pll_source_clk()
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| /u-boot/drivers/mmc/ |
| A D | meson_gx_mmc.c | 48 unsigned int clk, clk_src, clk_div; in meson_mmc_config_clock() local
58 clk_src = CLK_SRC_DIV2; in meson_mmc_config_clock()
61 clk_src = CLK_SRC_24M; in meson_mmc_config_clock()
80 meson_mmc_clk |= clk_src; in meson_mmc_config_clock()
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| /u-boot/drivers/spi/ |
| A D | mxc_spi.c | 197 u32 clk_src; in spi_cfg_mxc() local
202 clk_src = mxc_get_clock(MXC_CSPI_CLK); in spi_cfg_mxc()
204 div = DIV_ROUND_UP(clk_src, max_hz); in spi_cfg_mxc()
208 max_hz, div, clk_src / (4 << div)); in spi_cfg_mxc()
234 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); in spi_cfg_mxc() local
252 if (clk_src > max_hz) { in spi_cfg_mxc()
253 pre_div = (clk_src - 1) / max_hz; in spi_cfg_mxc()
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| /u-boot/drivers/video/nexell/soc/ |
| A D | s5pxx18_soc_disptop_clk.h | 37 u32 clk_src);
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| A D | s5pxx18_soc_disptop_clk.c | 152 u32 clk_src) in nx_disp_top_clkgen_set_clock_source() argument
164 read_value |= clk_src << clksrcsel_pos; in nx_disp_top_clkgen_set_clock_source()
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| A D | s5pxx18_soc_dpc.h | 200 void nx_dpc_set_clock_source(u32 module_index, u32 index, u32 clk_src);
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| A D | s5pxx18_soc_dpc.c | 252 void nx_dpc_set_clock_source(u32 module_index, u32 index, u32 clk_src) in nx_dpc_set_clock_source() argument
262 read_value |= clk_src << clksrcsel_pos; in nx_dpc_set_clock_source()
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| /u-boot/arch/arm/mach-imx/mx5/ |
| A D | clock.c | 798 u32 clk_src; in config_ddr_clk() local
808 clk_src = get_periph_clk(); in config_ddr_clk()
828 if ((clk_src % emi_clk) < 10000000) in config_ddr_clk()
829 div = clk_src / emi_clk; in config_ddr_clk()
831 div = (clk_src / emi_clk) + 1; in config_ddr_clk()
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| /u-boot/drivers/phy/marvell/ |
| A D | comphy_core.c | 144 comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode, in comphy_probe()
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| A D | comphy_cp110.c | 39 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
41 ((clk_src) << 17) | COMPHY_FW_FORMAT(mode, 0, speeds))
924 ptr_comphy_map->clk_src, in comphy_cp110_init()
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| /u-boot/drivers/clk/rockchip/ |
| A D | clk_px30.c | 423 u32 clk_src = priv->gpll_hz / 2; in px30_i2s_get_clk() local
444 return clk_src * n / m; in px30_i2s_get_clk()
449 u32 clk_src; in px30_i2s_set_clk() local
453 clk_src = priv->gpll_hz / 2; in px30_i2s_set_clk()
454 rational_best_approximation(hz, clk_src, in px30_i2s_set_clk()
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| /u-boot/arch/arm/cpu/armv7/bcm235xx/ |
| A D | clk-core.h | 67 struct clk_src *src;
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| /u-boot/arch/arm/cpu/armv7/bcm281xx/ |
| A D | clk-core.h | 67 struct clk_src *src;
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