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Searched refs:clrbits_le32 (Results 1 – 25 of 304) sorted by relevance

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/u-boot/drivers/ddr/altera/
A Dsdram_s10.c83 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG), in sdram_mmr_init_full()
85 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0), in sdram_mmr_init_full()
99 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0), in sdram_mmr_init_full()
101 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A), in sdram_mmr_init_full()
103 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B), in sdram_mmr_init_full()
105 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C), in sdram_mmr_init_full()
107 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D), in sdram_mmr_init_full()
113 clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0), in sdram_mmr_init_full()
306 clrbits_le32(plat->hmc + ECCCTRL1, in sdram_mmr_init_full()
318 clrbits_le32(plat->hmc + ECCCTRL1, in sdram_mmr_init_full()
[all …]
/u-boot/drivers/ram/rockchip/
A Dsdram_phy_px30.c21 clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3); in sdram_phy_dll_bypass_set()
25 clrbits_le32(PHY_REG(phy_base, j + 0x1), 1 << 3); in sdram_phy_dll_bypass_set()
32 clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); in sdram_phy_dll_bypass_set()
89 clrbits_le32(PHY_REG(phy_base, 0), 0x3 << 2); in phy_soft_reset()
105 clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3); in phy_dram_set_bw()
106 clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3); in phy_dram_set_bw()
109 clrbits_le32(PHY_REG(phy_base, 0x36), 1 << 3); in phy_dram_set_bw()
110 clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3); in phy_dram_set_bw()
111 clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3); in phy_dram_set_bw()
146 clrbits_le32(PHY_REG(phy_base, 2), 0x30); in phy_data_training()
[all …]
/u-boot/arch/arm/mach-davinci/
A Dda850_lowlevel.c41 clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK); in da850_pll_init()
47 clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC); in da850_pll_init()
49 clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC); in da850_pll_init()
52 clrbits_le32(&reg->pllctl, PLLCTL_PLLEN); in da850_pll_init()
67 clrbits_le32(&reg->pllctl, PLLCTL_PLLRST); in da850_pll_init()
77 clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN); in da850_pll_init()
80 clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS); in da850_pll_init()
174 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); in da850_ddr_setup()
176 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); in da850_ddr_setup()
192 clrbits_le32(&davinci_syscfg1_regs->ddr_slew, in da850_ddr_setup()
[all …]
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun50i_h616.c104 clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE); in mctl_sys_init()
105 clrbits_le32(&ccm->mbus_cfg, MBUS_RESET); in mctl_sys_init()
134 clrbits_le32(&mctl_com->unk_0x500, BIT(25)); in mctl_sys_init()
289 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4); in mctl_phy_write_leveling()
347 clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1); in mctl_phy_read_calibration()
755 clrbits_le32(&mctl_ctl->dfimisc, 0x20); in mctl_phy_init()
757 clrbits_le32(&mctl_ctl->pwrctl, 0x20); in mctl_phy_init()
763 clrbits_le32(&mctl_ctl->dfimisc, 1); in mctl_phy_init()
787 clrbits_le32(&mctl_ctl->rfshctl3, 1); in mctl_phy_init()
890 clrbits_le32(&mctl_ctl->dfimisc, BIT(0)); in mctl_ctrl_init()
[all …]
A Ddram_sun4i.c77 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
81 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
124 clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF); in mctl_itm_enable()
182 clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET | in mctl_enable_dllx()
300 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); in mctl_setup_dram_clock()
342 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); in mctl_setup_dram_clock()
392 clrbits_le32(&dram->csr, DRAM_CSR_FAILED); in dramc_scan_readpipe()
414 clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); in dramc_clock_output_en()
541 clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL); in mctl_set_impedance()
557 clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL); in mctl_set_impedance()
[all …]
A Dprcm.c42 clrbits_le32(&prcm->apb0_reset, flags); in prcm_apb0_disable()
45 clrbits_le32(&prcm->apb0_gate, flags); in prcm_apb0_disable()
A Ddram_sun50i_h6.c164 clrbits_le32(&ccm->dram_gate_reset, BIT(0)); in mctl_sys_init()
301 clrbits_le32(&mctl_com->cr, BIT(27)); in mctl_com_init()
378 clrbits_le32(&mctl_phy->pgcr[0], BIT(26)); in mctl_bit_delay_set()
434 clrbits_le32(&mctl_phy->pgcr[6], BIT(0)); in mctl_channel_init()
438 clrbits_le32(&mctl_phy->vtcr[1], BIT(1)); in mctl_channel_init()
455 clrbits_le32(&mctl_phy->dtcr[1], BIT(1)); in mctl_channel_init()
526 clrbits_le32(&mctl_phy->pgcr[6], 0xfff8); in mctl_channel_init()
544 clrbits_le32(&mctl_phy->pgcr[1], 0x40); in mctl_channel_init()
545 clrbits_le32(&mctl_ctl->dfimisc, BIT(0)); in mctl_channel_init()
548 clrbits_le32(&mctl_ctl->rfshctl3, BIT(0)); in mctl_channel_init()
[all …]
A Dclock.c62 clrbits_le32(&ccm->apb2_reset_cfg, in clock_twi_onoff()
64 clrbits_le32(&ccm->apb2_gate, in clock_twi_onoff()
/u-boot/arch/arm/mach-exynos/
A Dpower.c50 clrbits_le32(&power->usbhost_phy_control, in exynos5_set_usbhost_phy_ctrl()
70 clrbits_le32(&power->usbhost_phy_control, in exynos4412_set_usbhost_phy_ctrl()
72 clrbits_le32(&power->hsic1_phy_control, in exynos4412_set_usbhost_phy_ctrl()
74 clrbits_le32(&power->hsic2_phy_control, in exynos4412_set_usbhost_phy_ctrl()
99 clrbits_le32(&power->usbdrd_phy_control, in exynos5_set_usbdrd_phy_ctrl()
117 clrbits_le32(&power->usbdev_phy_control, in exynos5420_set_usbdev_phy_ctrl()
119 clrbits_le32(&power->usbdev1_phy_control, in exynos5420_set_usbdev_phy_ctrl()
A Dspl_boot.c78 clrbits_le32(&regs->ch_cfg, SPI_CH_RST); in spi_rx_tx()
127 clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ in exynos_spi_copy()
130 clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); in exynos_spi_copy()
138 clrbits_le32(&regs->ch_cfg, SPI_CH_RST); in exynos_spi_copy()
142 clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ in exynos_spi_copy()
168 clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD | in exynos_spi_copy()
177 clrbits_le32(&regs->ch_cfg, SPI_CH_RST); in exynos_spi_copy()
178 clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); in exynos_spi_copy()
/u-boot/drivers/usb/host/
A Dehci-exynos.c91 clrbits_le32(&usb->usbphyctrl0, in exynos5_setup_usb_phy()
108 clrbits_le32(&usb->usbphyctrl0, in exynos5_setup_usb_phy()
117 clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl); in exynos5_setup_usb_phy()
118 clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl); in exynos5_setup_usb_phy()
131 clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST | in exynos5_setup_usb_phy()
134 clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST | in exynos5_setup_usb_phy()
151 clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 | in exynos4412_setup_usb_phy()
157 clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST)); in exynos4412_setup_usb_phy()
A Dutmi-armada100.c29 clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK); in utmi_phy_init()
44 clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START); in utmi_phy_init()
49 clrbits_le32(&phy_regs->utmi_tx, RCAL_START); in utmi_phy_init()
A Dehci-tegra.c322 clrbits_le32(&usbctlr->port_sc1, STS1); in init_phy_mux()
326 clrbits_le32(&usbctlr->port_sc1, STS); in init_phy_mux()
341 clrbits_le32(&usbctlr->hostpc1_devlc, STS); in init_phy_mux()
433 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, in init_utmi_usb_controller()
467 clrbits_le32(&usbctlr->utmip_misc_cfg0, in init_utmi_usb_controller()
529 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, in init_utmi_usb_controller()
532 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, in init_utmi_usb_controller()
535 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, in init_utmi_usb_controller()
541 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); in init_utmi_usb_controller()
553 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); in init_utmi_usb_controller()
[all …]
/u-boot/drivers/clk/owl/
A Dclk_owl.c34 clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK); in owl_clk_init()
78 clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL); in owl_clk_enable()
86 clrbits_le32(priv->base + CMU_UART3CLK, CMU_UARTCLK_SRC_DEVPLL); in owl_clk_enable()
112 clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5); in owl_clk_disable()
118 clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3); in owl_clk_disable()
122 clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH); in owl_clk_disable()
/u-boot/arch/arm/mach-socfpga/
A Dfreeze_controller.c49 clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); in sys_mgr_frzctrl_freeze_req()
59 clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); in sys_mgr_frzctrl_freeze_req()
74 clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); in sys_mgr_frzctrl_freeze_req()
154 clrbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
197 clrbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
A Dreset_manager_arria10.c69 clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST, in socfpga_reset_deassert_noc_ddr_scheduler()
103 clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST, in socfpga_reset_deassert_bridges_handoff()
115 clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST, in socfpga_reset_deassert_osc1wd0()
152 clrbits_le32(socfpga_get_rstmgr_addr() + reg, in socfpga_per_reset()
/u-boot/drivers/usb/dwc3/
A Dsamsung_usb_phy.c22 clrbits_le32(&phy->phy_param0, in exynos5_usb3_phy_init()
41 clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK); in exynos5_usb3_phy_init()
47 clrbits_le32(&phy->phy_test, in exynos5_usb3_phy_init()
/u-boot/drivers/fpga/
A Dsocfpga_gen5.c57 clrbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_program_init()
73 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); in fpgamgr_program_init()
94 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); in fpgamgr_program_init()
146 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); in fpgamgr_program_poll_cd()
194 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); in fpgamgr_program_poll_usermode()
/u-boot/arch/arm/cpu/arm926ejs/mxs/
A Dspl_power_init.c399 clrbits_le32(&power_regs->hw_power_5vctrl, in mxs_enable_4p2_dcdc_input()
409 clrbits_le32(&power_regs->hw_power_5vctrl, in mxs_enable_4p2_dcdc_input()
451 clrbits_le32(&power_regs->hw_power_ctrl, in mxs_enable_4p2_dcdc_input()
499 clrbits_le32(&power_regs->hw_power_dcdc4p2, in mxs_power_init_4p2_regulator()
576 clrbits_le32(&power_regs->hw_power_dcdc4p2, in mxs_power_init_dcdc_4p2_source()
620 clrbits_le32(&power_regs->hw_power_dcdc4p2, in mxs_power_enable_4p2()
720 clrbits_le32(&power_regs->hw_power_dcdc4p2, in mxs_batt_boot()
736 clrbits_le32(&power_regs->hw_power_vdddctrl, in mxs_batt_boot()
739 clrbits_le32(&power_regs->hw_power_vddactrl, in mxs_batt_boot()
885 clrbits_le32(&power_regs->hw_power_vdddctrl, in mxs_switch_vddd_to_dcdc_source()
[all …]
A Dspl_mem_init.c261 clrbits_le32(&power_regs->hw_power_vddmemctrl, in mx23_mem_setup_vddmem()
286 clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8)); in mx23_mem_init()
293 clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); in mx23_mem_init()
328 clrbits_le32(MXS_DRAM_BASE + 0x40, 1); in mx28_mem_init()
333 clrbits_le32(MXS_DRAM_BASE + 0x44, 1); in mx28_mem_init()
/u-boot/drivers/ddr/imx/imx8m/
A Dddr_init.c55 clrbits_le32(DDRC_SBRCTL(0), 0x1); in ddrc_inline_ecc_scrub()
78 clrbits_le32(DDRC_SBRCTL(0), 0x1); in ddrc_inline_ecc_scrub_end()
160 clrbits_le32(DDRC_DFIMISC(0), 0x1); in ddr_init()
214 clrbits_le32(DDRC_DFIMISC(0), (0x1 << 5)); in ddr_init()
222 clrbits_le32(DDRC_PWRCTL(0), (0x1 << 5)); in ddr_init()
/u-boot/board/kmc/kzm9g/
A Dkzm9g.c155 clrbits_le32(&cpg->smstpcr3, (1 << 15)); in s_init()
156 clrbits_le32(&cpg_srcr->srcr3, (1 << 15)); in s_init()
157 clrbits_le32(&cpg->smstpcr2, (1 << 18)); in s_init()
158 clrbits_le32(&cpg_srcr->srcr2, (1 << 18)); in s_init()
170 clrbits_le32(&cpg->smstpcr0, (1 << 1)); in s_init()
172 clrbits_le32(&cpg_srcr->srcr0, (1 << 1)); in s_init()
238 clrbits_le32(&cpg->pllecr, (1 << 3)); in s_init()
276 clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); in board_early_init_f()
277 clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); in board_early_init_f()
278 clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); in board_early_init_f()
[all …]
/u-boot/board/hisilicon/poplar/
A Dpoplar.c142 clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ); in usb2_phy_init()
148 clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1); in usb2_phy_init()
158 clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ | in usb2_phy_init()
/u-boot/arch/arm/cpu/armv7/sunxi/
A Dpsci.c111 clrbits_le32(pwroff, BIT(cpu)); in sunxi_power_switch()
186 clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu)); in sunxi_cpu_power_off()
263 clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu)); in psci_cpu_on()
266 clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu)); in psci_cpu_on()
298 clrbits_le32(GICD_BASE + GICD_IGROUPRn, BIT(15)); in psci_arch_init()
/u-boot/board/solidrun/clearfog/
A Dclearfog.c206 clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); in board_init()
207 clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9)); in board_init()
209 clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19)); in board_init()
210 clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19)); in board_init()

Completed in 46 milliseconds

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