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Searched refs:cru (Results 1 – 25 of 115) sorted by relevance

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/u-boot/drivers/clk/rockchip/
A Dclk_rv1108.c199 val = readl(&cru->clksel_con[22]); in rv1108_saradc_get_clk()
213 rk_clrsetreg(&cru->clksel_con[22], in rv1108_saradc_set_clk()
217 return rv1108_saradc_get_clk(cru); in rv1108_saradc_set_clk()
224 val = readl(&cru->clksel_con[28]); in rv1108_aclk_vio1_get_clk()
238 rk_clrsetreg(&cru->clksel_con[28], in rv1108_aclk_vio1_set_clk()
250 val = readl(&cru->clksel_con[28]); in rv1108_aclk_vio0_get_clk()
264 rk_clrsetreg(&cru->clksel_con[28], in rv1108_aclk_vio0_set_clk()
270 rk_clrsetreg(&cru->clksel_con[29], in rv1108_aclk_vio0_set_clk()
314 val = readl(&cru->clksel_con[2]); in rv1108_aclk_bus_get_clk()
329 rk_clrsetreg(&cru->clksel_con[2], in rv1108_aclk_bus_set_clk()
[all …]
A Dclk_rk3308.c71 struct rk3308_cru *cru = priv->cru; in rk3308_armclk_set_clk() local
131 struct rk3308_cru *cru = priv->cru; in rk3308_i2c_get_clk() local
161 struct rk3308_cru *cru = priv->cru; in rk3308_i2c_set_clk() local
195 struct rk3308_cru *cru = priv->cru; in rk3308_mac_set_clk() local
225 struct rk3308_cru *cru = priv->cru; in rk3308_mac_set_speed_clk() local
241 struct rk3308_cru *cru = priv->cru; in rk3308_mmc_get_clk() local
271 struct rk3308_cru *cru = priv->cru; in rk3308_mmc_set_clk() local
313 struct rk3308_cru *cru = priv->cru; in rk3308_saradc_get_clk() local
325 struct rk3308_cru *cru = priv->cru; in rk3308_saradc_set_clk() local
341 struct rk3308_cru *cru = priv->cru; in rk3308_tsadc_get_clk() local
[all …]
A Dclk_rk3288.c400 val = readl(&cru->cru_clksel_con[8]); in rockchip_i2s_get_clk()
422 &cru->cru_clksel_con[8]); in rockchip_i2s_set_clk()
435 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
464 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
496 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
557 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
747 return rockchip_saradc_get_clk(cru); in rockchip_saradc_set_clk()
795 struct rockchip_cru *cru = priv->cru; in rk3288_clk_set_rate() local
902 struct rockchip_cru *cru = priv->cru; in rk3288_gmac_set_parent() local
963 priv->cru = dev_read_addr_ptr(dev); in rk3288_clk_of_to_plat()
[all …]
A Dclk_rk3399.c454 rk_clrsetreg(&cru->clksel_con[0], in rk3399_configure_cpu_l()
461 rk_clrsetreg(&cru->clksel_con[1], in rk3399_configure_cpu_l()
489 rk_clrsetreg(&cru->clksel_con[2], in rk3399_configure_cpu_b()
496 rk_clrsetreg(&cru->clksel_con[3], in rk3399_configure_cpu_b()
525 con = readl(&cru->clksel_con[61]); in rk3399_i2c_get_clk()
529 con = readl(&cru->clksel_con[62]); in rk3399_i2c_get_clk()
533 con = readl(&cru->clksel_con[63]); in rk3399_i2c_get_clk()
892 val = readl(&cru->clksel_con[26]); in rk3399_saradc_get_clk()
906 rk_clrsetreg(&cru->clksel_con[26], in rk3399_saradc_set_clk()
910 return rk3399_saradc_get_clk(cru); in rk3399_saradc_set_clk()
[all …]
A Dclk_rk3328.c221 pll_con = cru->apll_con; in rkclk_set_pll()
225 pll_con = cru->dpll_con; in rkclk_set_pll()
229 pll_con = cru->cpll_con; in rkclk_set_pll()
233 pll_con = cru->gpll_con; in rkclk_set_pll()
237 pll_con = cru->npll_con; in rkclk_set_pll()
301 rk_clrsetreg(&cru->clksel_con[28], in rkclk_init()
305 rk_clrsetreg(&cru->clksel_con[29], in rkclk_init()
324 rk_clrsetreg(&cru->clksel_con[0], in rk3328_configure_cpu()
329 rk_clrsetreg(&cru->clksel_con[1], in rk3328_configure_cpu()
581 return rk3328_spi_get_clk(cru); in rk3328_spi_set_clk()
[all …]
A Dclk_px30.c291 struct px30_cru *cru = priv->cru; in px30_i2c_get_clk() local
321 struct px30_cru *cru = priv->cru; in px30_i2c_set_clk() local
425 struct px30_cru *cru = priv->cru; in px30_i2s_get_clk() local
451 struct px30_cru *cru = priv->cru; in px30_i2s_set_clk() local
482 struct px30_cru *cru = priv->cru; in px30_nandc_get_clk() local
494 struct px30_cru *cru = priv->cru; in px30_nandc_set_clk() local
514 struct px30_cru *cru = priv->cru; in px30_mmc_get_clk() local
544 struct px30_cru *cru = priv->cru; in px30_mmc_set_clk() local
586 struct px30_cru *cru = priv->cru; in px30_pwm_get_clk() local
608 struct px30_cru *cru = priv->cru; in px30_pwm_set_clk() local
[all …]
A Dclk_rk3188.c213 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_configure_cpu()
218 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_configure_cpu()
243 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
272 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
383 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
407 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
420 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
443 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
453 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
503 struct rk3188_cru *cru = priv->cru; in rk3188_clk_set_rate() local
[all …]
A Dclk_rk3128.c151 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
171 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
176 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
194 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
199 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
228 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
260 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
384 rk_setreg(&cru->cru_clksel_con[10], in rk3128_peri_set_pclk()
417 return rk3128_saradc_get_clk(cru); in rk3128_saradc_set_clk()
554 priv->cru = dev_read_addr_ptr(dev); in rk3128_clk_of_to_plat()
[all …]
A Dclk_rk322x.c92 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
112 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
117 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
135 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
140 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
169 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
194 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
410 struct rk322x_cru *cru = priv->cru; in rk322x_gmac_set_parent() local
439 struct rk322x_cru *cru = priv->cru; in rk322x_gmac_extclk_set_parent() local
483 priv->cru = dev_read_addr_ptr(dev); in rk322x_clk_of_to_plat()
[all …]
A Dclk_rk3368.c152 dpll = rkclk_pll_get_rate(cru, DPLL); in rkclk_init()
153 cpll = rkclk_pll_get_rate(cru, CPLL); in rkclk_init()
154 gpll = rkclk_pll_get_rate(cru, GPLL); in rkclk_init()
257 struct rk3368_cru *cru = priv->cru; in rk3368_mmc_set_clk() local
310 rkclk_set_pll(cru, DPLL, dpll_cfg); in rk3368_ddr_set_clk()
436 val = readl(&cru->clksel_con[25]); in rk3368_saradc_get_clk()
450 rk_clrsetreg(&cru->clksel_con[25], in rk3368_saradc_set_clk()
454 return rk3368_saradc_get_clk(cru); in rk3368_saradc_set_clk()
529 struct rk3368_cru *cru = priv->cru; in rk3368_gmac_set_parent() local
591 rkclk_init(priv->cru); in rk3368_clk_probe()
[all …]
A Dclk_rk3036.c90 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
110 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
115 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
133 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
138 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
158 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
167 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
192 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
225 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
326 priv->cru = dev_read_addr_ptr(dev); in rk3036_clk_of_to_plat()
[all …]
/u-boot/arch/arm/dts/
A Drk3288.dtsi205 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
226 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
414 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
416 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
481 rockchip,cru = <&cru>;
611 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
612 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
613 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
670 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
714 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
[all …]
A Drk3399.dtsi238 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
280 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
1300 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1302 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1356 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1363 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1595 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1599 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1652 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1656 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
[all …]
A Drk3xxx.dtsi121 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
132 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
179 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
191 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
201 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
211 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
232 rockchip,cru = <&cru>;
366 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
377 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
393 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
[all …]
A Drk3328.dtsi281 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
684 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
686 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
779 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
780 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
781 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
788 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
789 <&cru SCLK_WIFI>, <&cru ARMCLK>,
790 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
793 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
[all …]
A Drk322x.dtsi133 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
148 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
161 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
178 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
192 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
206 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
405 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
419 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
449 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
450 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
[all …]
A Dpx30.dtsi369 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
384 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
541 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
554 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
567 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
581 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
596 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
902 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
903 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
1021 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
[all …]
A Drk3036.dtsi54 clocks = <&cru ARMCLK>;
117 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
130 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
143 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
155 clocks = <&cru PCLK_PWM>;
166 clocks = <&cru PCLK_PWM>;
177 clocks = <&cru PCLK_PWM>;
188 clocks = <&cru PCLK_PWM>;
246 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
247 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
[all …]
A Drv1108.dtsi88 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
102 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
116 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
161 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
187 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
199 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
211 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
257 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
271 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
272 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
[all …]
A Drk3308.dtsi192 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
205 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
218 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
231 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
320 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
336 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
352 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
368 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
379 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
638 <&cru SCLK_MAC>, <&cru ACLK_MAC>,
[all …]
A Drk3128.dtsi235 <&cru HCLK_NANDC>,
236 <&cru SRST_NANDC>;
264 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
279 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
294 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
307 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
445 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
446 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
461 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
462 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
[all …]
A Drk3368.dtsi233 rockchip,cru = <&cru>;
250 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
262 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
274 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
295 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
308 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
321 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
387 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
531 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
532 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
[all …]
/u-boot/doc/device-tree-bindings/clock/
A Drockchip,rk3188-cru.txt9 - compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
10 "rockchip,rk3066a-cru"
23 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
24 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
42 cru: cru@20000000 {
43 compatible = "rockchip,rk3188-cru";
60 clocks = <&cru SCLK_UART0>;
/u-boot/arch/arm/mach-rockchip/
A Dcpu-info.c18 struct rockchip_cru *cru = rockchip_get_cru(); in get_reset_cause() local
21 if (IS_ERR(cru)) in get_reset_cause()
24 switch (cru->glb_rst_st) { in get_reset_cause()
/u-boot/arch/arm/mach-rockchip/rk3368/
A Drk3368.c69 struct rk3368_cru *cru = rockchip_get_cru(); in mcu_init() local
84 rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK, in mcu_init()
89 rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK); in mcu_init()
128 struct rk3368_cru * const cru = in sgrf_init() local
153 rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ); in sgrf_init()
154 rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ); in sgrf_init()
159 rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ); in sgrf_init()
160 rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); in sgrf_init()

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