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Searched refs:cs_ena (Results 1 – 13 of 13) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_spd.c653 cs_ena = 0;
665 cs_ena |= (0x1 << cs);
667 cs_ena |= (0x3 << cs);
669 cs_ena |= (0x7 << cs);
671 cs_ena |= (0xF << cs);
681 if (cs_ena > 0xF) {
937 if (cs_ena & (1 << cs))
972 reg = odt_config[cs_ena];
980 reg = cs_ena;
1037 if (cs_ena & (1 << cs))
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A Dddr3_write_leveling.c109 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw()
231 if (dram_info->cs_ena & (1 << cs)) { in ddr3_wl_supplement()
433 if (dram_info->cs_ena & (1 << cs)) { in ddr3_wl_supplement()
532 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw_reg_dimm()
621 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw_reg_dimm()
681 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
724 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
839 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
916 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw_reg_dimm()
957 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw_reg_dimm()
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A Dddr3_hw_training.c96 dram_info.cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_hw_training()
230 if (dram_info.cs_ena > 1) { in ddr3_hw_training()
321 if (dram_info.cs_ena > 1) { in ddr3_hw_training()
457 dram_info.cs_ena = 1; in ddr3_hw_training()
667 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_load_patterns()
715 tmp_cs = dram_info->cs_ena; in ddr3_save_training()
893 dram_info->cs_ena = 0x1; in ddr3_check_if_resume_mode()
902 dram_info->cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_check_if_resume_mode()
958 dram_info->cs_ena = 1; in ddr3_training_suspend_resume()
1091 u32 cs_ena, reg; in ddr3_odt_read_dynamic_config() local
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A Dddr3_init.c144 u32 cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_restore_and_set_final_windows() local
171 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
187 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
200 u32 cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_save_and_set_training_windows() local
234 if (cs_ena & (1 << cs)) { in ddr3_save_and_set_training_windows()
1070 u32 cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_get_cs_num_from_reg() local
1075 if (cs_ena & (1 << cs)) in ddr3_get_cs_num_from_reg()
A Dddr3_dfs.c197 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
443 if (dram_info->cs_ena & (1 << cs)) in ddr3_dfs_high_2_low()
469 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
677 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
1006 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_low_2_high()
1010 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_dfs_low_2_high()
1138 if (dram_info->cs_ena & (1 << cs)) in ddr3_dfs_low_2_high()
1164 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_low_2_high()
1437 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_low_2_high()
A Dddr3_dqs.c152 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dqs_centralization_rx()
234 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dqs_centralization_tx()
335 if (dram_info->cs_ena & (1 << cs_tmp)) in ddr3_find_adll_limits()
1336 if (dram_info->cs_ena & (1 << cs)) { in ddr3_load_dqs_patterns()
1339 if (dram_info->cs_ena & (1 << cs_tmp)) in ddr3_load_dqs_patterns()
A Dxor.c52 if (dram_info->cs_ena & (1 << ui)) { in mv_sys_xor_init()
A Dddr3_read_leveling.c75 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
99 if (dram_info->cs_ena & (1 << cs)) { in ddr3_read_leveling_hw()
197 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_read_leveling_sw()
A Dddr3_hw_training.h253 u32 cs_ena; member
A Dddr3_pbs.c1561 if (dram_info->cs_ena & (1 << cs)) { in ddr3_load_pbs_patterns()
1564 if (dram_info->cs_ena & (1 << cs_tmp)) in ddr3_load_pbs_patterns()
/u-boot/drivers/ddr/marvell/a38x/
A Dxor.c21 void mv_sys_xor_init(u32 num_of_cs, u32 cs_ena, uint64_t cs_size, u32 base_delta) in mv_sys_xor_init() argument
38 if (cs_ena & (1 << ui)) { in mv_sys_xor_init()
52 if (cs_ena & (1 << ui)) { in mv_sys_xor_init()
342 u32 cs_ena = 0; in ddr3_new_tip_ecc_scrub() local
348 cs_ena |= 1 << cs_c; in ddr3_new_tip_ecc_scrub()
353 mv_sys_xor_init(max_cs, cs_ena, cs_mem_size, 0); in ddr3_new_tip_ecc_scrub()
A Dmv_ddr_plat.c1016 static int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena) in ddr3_fast_path_dynamic_cs_size_config() argument
1033 if (cs_ena & (1 << cs)) { in ddr3_fast_path_dynamic_cs_size_config()
1104 u32 cs_ena = mv_ddr_sys_env_get_cs_ena_from_reg(); in ddr3_restore_and_set_final_windows() local
1118 if (ddr3_fast_path_dynamic_cs_size_config(cs_ena) != MV_OK) in ddr3_restore_and_set_final_windows()
1124 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
1138 u32 cs_ena; in ddr3_save_and_set_training_windows() local
1157 cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask; in ddr3_save_and_set_training_windows()
1171 if (cs_ena & (1 << cs)) { in ddr3_save_and_set_training_windows()
A Dddr3_init.h173 void ddr3_fast_path_static_cs_size_config(u32 cs_ena);

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