| /u-boot/arch/mips/mach-ath79/ar934x/ |
| A D | ddr.c | 45 u32 reg, cycle, ctl; in ar934x_ddr_init() local
54 cycle = 0xffff; in ar934x_ddr_init()
60 cycle = 0xff; in ar934x_ddr_init()
62 cycle = 0xffff; in ar934x_ddr_init()
66 cycle = 0xffff; /* DDR2 16bit */ in ar934x_ddr_init()
83 cycle = 0xffffffff; in ar934x_ddr_init()
150 writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE); in ar934x_ddr_init()
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| /u-boot/drivers/pwm/ |
| A D | Kconfig | 6 control over the duty cycle (high and low time) of the signal. This
17 supports a programmable period and duty cycle. A 32-bit counter is
31 programmable period and duty cycle for 2 independant channels.
38 programmable period and duty cycle.
45 programmable period and duty cycle. A 32-bit counter is used.
68 four channels with a programmable period and duty cycle. Only a
69 32KHz clock is supported by the driver but the duty cycle is
77 programmable period and duty cycle. A 16-bit counter is used.
|
| /u-boot/board/buffalo/lsxl/ |
| A D | kwbimage-lschl.cfg | 38 # bit4: 0, addr/cmd in same cycle
55 # bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0])
56 # bit7-4: 4, 5 cycle tRCD
60 # bit20: 0, 16 cycle tRAS (tRAS[4])
62 # bit27-24: 3, 4 cycle tRRD
67 # bit6-0: 0x23, 35 cycle tRFC
68 # bit8-7: 0, 1 cycle tR2R
130 # bit9: 0, no half clock cycle addition to dataout
131 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
132 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
|
| A D | kwbimage-lsxhl.cfg | 55 # bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0])
56 # bit7-4: 4, 5 cycle tRCD
60 # bit20: 1, 18 cycle tRAS (tRAS[4])
62 # bit27-24: 2, 3 cycle tRRD
67 # bit6-0: 0x32, 50 cycle tRFC
68 # bit8-7: 0, 1 cycle tR2R
130 # bit9: 0, no half clock cycle addition to dataout
131 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
132 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
|
| /u-boot/arch/arm/dts/ |
| A D | sun50i-a64-pinephone-1.1.dts | 17 * 1.0, and the lowest PWM duty cycle that doesn't lead to backlight
18 * being off is around 20%. Duty cycle for the lowest brightness level
|
| A D | sun50i-a64-pinephone-1.2.dts | 17 * and the lowest PWM duty cycle that doesn't lead to backlight being off
18 * is around 10%. Duty cycle for the lowest brightness level also varries
|
| A D | omap-gpmc-smsc911x.dtsi | 40 gpmc,rd-cycle-ns = <155>;
41 gpmc,wr-cycle-ns = <155>;
|
| A D | omap-gpmc-smsc9221.dtsi | 42 gpmc,rd-cycle-ns = <60>;
43 gpmc,wr-cycle-ns = <54>;
|
| A D | imx7d-sdb-qspi.dts | 40 /* take off one dummy cycle */
|
| A D | omap3-evm.dts | 81 gpmc,rd-cycle-ns = <82>;
82 gpmc,wr-cycle-ns = <82>;
|
| A D | omap3-igep.dtsi | 132 gpmc,rd-cycle-ns = <82>;
133 gpmc,wr-cycle-ns = <82>;
165 gpmc,rd-cycle-ns = <114>;
166 gpmc,wr-cycle-ns = <114>;
|
| /u-boot/board/d-link/dns325/ |
| A D | kwbimage.cfg | 36 # bit4: 0, addr/cmd in smame cycle
52 # bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
53 # bit7-4: 5, 6 cycle tRCD
57 # bit20: 1, 18 cycle tRAS (tRAS[4])
59 # bit27-24: 2, 3 cycle tRRD
63 # bit6-0: 0x33, 33 cycle tRFC
64 # bit8-7: 0, 1 cycle tR2R
120 # bit9: 0, no half clock cycle addition to dataout
121 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
122 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
|
| /u-boot/board/atmel/at91sam9261ek/ |
| A D | at91sam9261ek.c | 58 &smc->cs[3].cycle); in at91sam9261ek_nand_hw_init()
67 &smc->cs[3].cycle); in at91sam9261ek_nand_hw_init()
106 &smc->cs[2].cycle); in at91sam9261ek_dm9000_hw_init()
120 &smc->cs[2].cycle); in at91sam9261ek_dm9000_hw_init()
|
| /u-boot/tools/concurrencytest/ |
| A D | concurrencytest.py | 27 from itertools import cycle
111 for partition, test in zip(cycle(partitions), tests):
|
| /u-boot/board/ronetix/pm9261/ |
| A D | pm9261.c | 57 &smc->cs[3].cycle); in pm9261_nand_hw_init()
99 &smc->cs[2].cycle); in pm9261_dm9000_hw_init()
|
| /u-boot/doc/device-tree-bindings/video/ |
| A D | intel-gma.txt | 15 - intel,panel-power-cycle-delay : T4 time sequence (6 = 500ms)
33 intel,panel-power-cycle-delay = <6>;
|
| /u-boot/board/Seagate/nas220/ |
| A D | kwbimage.cfg | 36 # bit 4: 0=addr/cmd in smame cycle
116 # bit9 : 0 , no half clock cycle addition to dataout
117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
118 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
| /u-boot/board/Marvell/dreamplug/ |
| A D | kwbimage.cfg | 32 # bit 4: 0=addr/cmd in smame cycle
111 # bit9 : 0 , no half clock cycle addition to dataout
112 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
113 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
| /u-boot/board/Marvell/guruplug/ |
| A D | kwbimage.cfg | 31 # bit 4: 0=addr/cmd in smame cycle
110 # bit9 : 0 , no half clock cycle addition to dataout
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
112 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
| /u-boot/board/Marvell/sheevaplug/ |
| A D | kwbimage.cfg | 31 # bit 4: 0=addr/cmd in smame cycle
110 # bit9 : 0 , no half clock cycle addition to dataout
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
112 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
| /u-boot/board/Synology/ds109/ |
| A D | kwbimage.cfg | 35 # bit 4: 0=addr/cmd in smame cycle
114 # bit9 : 0 , no half clock cycle addition to dataout
115 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
116 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
| /u-boot/board/Seagate/dockstar/ |
| A D | kwbimage.cfg | 34 # bit 4: 0=addr/cmd in smame cycle
113 # bit9 : 0 , no half clock cycle addition to dataout
114 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
115 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
| /u-boot/board/Seagate/goflexhome/ |
| A D | kwbimage.cfg | 37 # bit 4: 0=addr/cmd in smame cycle
116 # bit9 : 0 , no half clock cycle addition to dataout
117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
118 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
|
| /u-boot/board/keymile/km_arm/ |
| A D | kwbimage-memphis.cfg | 55 # bit 4: 0=addr/cmd in smame cycle
125 # bit9 : 0 , no half clock cycle addition to dataout
126 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
127 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
140 # bit3-0 : 0001, M_ODT assertion same cycle as write
|
| /u-boot/board/esd/meesc/ |
| A D | meesc.c | 79 &smc->cs[3].cycle); in meesc_nand_hw_init()
121 &smc1->cs[0].cycle); in meesc_ethercat_hw_init()
|