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Searched refs:ddrc_cfg (Results 1 – 21 of 21) sorted by relevance

/u-boot/drivers/ddr/imx/imx8m/
A Dddr_init.c14 void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) in ddr_cfg_umctl2() argument
19 reg32_write(ddrc_cfg->reg, ddrc_cfg->val); in ddr_cfg_umctl2()
20 ddrc_cfg++; in ddr_cfg_umctl2()
129 ddr_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); in ddr_init()
A Dhelper.c152 saved_timing->ddrc_cfg = cfg; in dram_config_save()
154 cfg->reg = timing_info->ddrc_cfg[i].reg; in dram_config_save()
155 cfg->val = timing_info->ddrc_cfg[i].val; in dram_config_save()
/u-boot/board/gateworks/venice/
A Dlpddr4_timing.c1978 .ddrc_cfg = lpddr4_ddrc_cfg_1gb,
2494 .ddrc_cfg = lpddr4_ddrc_cfg_4gb,
/u-boot/arch/mips/mach-jz47xx/jz4780/
A Dsdram.c48 u32 ddrc_cfg, tmp; in ddr_cfg_init() local
56 ddrc_cfg = DDRC_CFG_TYPE_DDR3 | DDRC_CFG_IMBA | in ddr_cfg_init()
64 ddrc_cfg |= BIT(21); in ddr_cfg_init()
66 writel(ddrc_cfg, ddr_ctl_regs + DDRC_CFG); in ddr_cfg_init()
/u-boot/board/google/imx8mq_phanbell/
A Dlpddr4_timing_1g.c1720 .ddrc_cfg = ddr_ddrc_cfg,
/u-boot/board/technexion/pico-imx8mq/
A Dlpddr4_timing_1gb.c1722 .ddrc_cfg = ddr_ddrc_cfg,
A Dlpddr4_timing_2gb.c1722 .ddrc_cfg = ddr_ddrc_cfg,
A Dlpddr4_timing_3gb.c1722 .ddrc_cfg = ddr_ddrc_cfg,
A Dlpddr4_timing_4gb.c1722 .ddrc_cfg = ddr_ddrc_cfg,
/u-boot/board/freescale/imx8mn_evk/
A Dddr4_timing.c1202 .ddrc_cfg = ddr_ddrc_cfg,
/u-boot/board/beacon/imx8mn/
A Dlpddr4_timing.c1422 .ddrc_cfg = ddr_ddrc_cfg,
A Dlpddr4_2g_timing.c1429 .ddrc_cfg = ddr_ddrc_cfg,
/u-boot/board/phytec/phycore_imx8mm/
A Dlpddr4_timing.c1835 .ddrc_cfg = ddr_ddrc_cfg,
/u-boot/board/phytec/phycore_imx8mp/
A Dlpddr4_timing.c1838 .ddrc_cfg = ddr_ddrc_cfg,
/u-boot/board/freescale/imx8mp_evk/
A Dlpddr4_timing.c1837 .ddrc_cfg = ddr_ddrc_cfg,
/u-boot/board/toradex/verdin-imx8mm/
A Dlpddr4_timing.c1839 .ddrc_cfg = ddr_ddrc_cfg,
/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c1970 .ddrc_cfg = lpddr4_ddrc_cfg,
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c1970 .ddrc_cfg = lpddr4_ddrc_cfg,
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c1178 .ddrc_cfg = lpddr4_ddrc_cfg,
A Dlpddr4_timing.c1315 .ddrc_cfg = lpddr4_ddrc_cfg,
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h687 struct dram_cfg_param *ddrc_cfg; member

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