| /u-boot/drivers/ram/ |
| A D | mpc83xx_sdram.c | 413 ddr_type = dev_read_u32_default(dev, "ddr_type", 0); in mpc83xx_sdram_probe()
420 mvref_sel = dev_read_u32_default(dev, "mvref_sel", 0); in mpc83xx_sdram_probe()
427 m_odr = dev_read_u32_default(dev, "m_odr", 0); in mpc83xx_sdram_probe()
668 dev_read_u32_default(dev, "activate_to_activate", 0); in mpc83xx_sdram_probe()
802 ecc = dev_read_u32_default(dev, "ecc", 0); in mpc83xx_sdram_probe()
868 timing_2t = dev_read_u32_default(dev, "timing_2t", 0); in mpc83xx_sdram_probe()
951 dll_reset = dev_read_u32_default(dev, "dll_reset", 0); in mpc83xx_sdram_probe()
1000 sdmode = dev_read_u32_default(dev, "sdmode", 0); in mpc83xx_sdram_probe()
1007 esdmode = dev_read_u32_default(dev, "esdmode", 0); in mpc83xx_sdram_probe()
1018 esdmode2 = dev_read_u32_default(dev, "esdmode2", 0); in mpc83xx_sdram_probe()
[all …]
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| /u-boot/drivers/mmc/ |
| A D | nexell_dw_mmc.c | 154 host->buswidth = dev_read_u32_default(dev, "bus-width", 4); in nexell_dwmmc_of_to_plat()
159 val = dev_read_u32_default(dev, "index", -1); in nexell_dwmmc_of_to_plat()
166 priv->fifo_size = dev_read_u32_default(dev, "fifo-size", 0x20); in nexell_dwmmc_of_to_plat()
168 priv->frequency = dev_read_u32_default(dev, "frequency", 50000000); in nexell_dwmmc_of_to_plat()
169 priv->max_freq = dev_read_u32_default(dev, "max-frequency", 50000000); in nexell_dwmmc_of_to_plat()
171 priv->d_delay = dev_read_u32_default(dev, "drive_dly", 0); in nexell_dwmmc_of_to_plat()
172 priv->d_shift = dev_read_u32_default(dev, "drive_shift", 3); in nexell_dwmmc_of_to_plat()
173 priv->s_delay = dev_read_u32_default(dev, "sample_dly", 0); in nexell_dwmmc_of_to_plat()
174 priv->s_shift = dev_read_u32_default(dev, "sample_shift", 2); in nexell_dwmmc_of_to_plat()
175 priv->mmcboost = dev_read_u32_default(dev, "mmcboost", 0); in nexell_dwmmc_of_to_plat()
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| A D | ca_dw_mmc.c | 102 host->buswidth = dev_read_u32_default(dev, "bus-width", 1); in ca_dwmmc_of_to_plat()
103 host->bus_hz = dev_read_u32_default(dev, "max-frequency", 50000000); in ca_dwmmc_of_to_plat()
104 priv->ds = dev_read_u32_default(dev, "io_ds", 0x33); in ca_dwmmc_of_to_plat()
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| A D | rockchip_dw_mmc.c | 61 host->buswidth = dev_read_u32_default(dev, "bus-width", 4); in rockchip_dwmmc_of_to_plat()
71 priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); in rockchip_dwmmc_of_to_plat()
87 int val = dev_read_u32_default(dev, "max-frequency", -EINVAL); in rockchip_dwmmc_of_to_plat()
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| A D | rockchip_sdhci.c | 51 max_frequency = dev_read_u32_default(dev, "max-frequency", 0); in arasan_sdhci_probe()
91 host->bus_width = dev_read_u32_default(dev, "bus-width", 4); in arasan_sdhci_of_to_plat()
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| /u-boot/drivers/video/ |
| A D | sandbox_sdl.c | 57 plat->xres = dev_read_u32_default(dev, "xres", LCD_MAX_WIDTH); in sandbox_sdl_bind()
58 plat->yres = dev_read_u32_default(dev, "yres", LCD_MAX_HEIGHT); in sandbox_sdl_bind()
59 plat->bpix = dev_read_u32_default(dev, "log2-depth", VIDEO_BPP16); in sandbox_sdl_bind()
60 plat->rot = dev_read_u32_default(dev, "rotate", 0); in sandbox_sdl_bind()
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| /u-boot/drivers/led/ |
| A D | led_cortina.c | 142 dev_read_u32_default(dev, "Cortina,blink-rate1", 256); in ca_led_of_to_plat()
144 dev_read_u32_default(dev, "Cortina,blink-rate2", 512); in ca_led_of_to_plat()
150 priv->pin = dev_read_u32_default(dev, "pin", LED_MAX_COUNT); in ca_led_of_to_plat()
151 priv->blink_sel = dev_read_u32_default(dev, "blink-sel", 0); in ca_led_of_to_plat()
152 priv->off_event = dev_read_u32_default(dev, "off-event", 0); in ca_led_of_to_plat()
153 priv->blink_event = dev_read_u32_default(dev, "blink-event", 0); in ca_led_of_to_plat()
154 priv->on_event = dev_read_u32_default(dev, "on-event", 0); in ca_led_of_to_plat()
155 priv->port = dev_read_u32_default(dev, "port", 0); in ca_led_of_to_plat()
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| A D | led_bcm6358.c | 130 clk_div = dev_read_u32_default(dev, "brcm,clk-div", in bcm6358_led_probe()
159 pin = dev_read_u32_default(dev, "reg", LEDS_MAX); in bcm6358_led_probe()
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| /u-boot/drivers/gpio/ |
| A D | xilinx_gpio.c | 273 plat->bank_max[0] = dev_read_u32_default(dev, "xlnx,gpio-width", 0); in xilinx_gpio_of_to_plat()
274 plat->bank_input[0] = dev_read_u32_default(dev, "xlnx,all-inputs", 0); in xilinx_gpio_of_to_plat()
275 plat->bank_output[0] = dev_read_u32_default(dev, "xlnx,all-outputs", 0); in xilinx_gpio_of_to_plat()
276 plat->dout_default[0] = dev_read_u32_default(dev, "xlnx,dout-default", in xilinx_gpio_of_to_plat()
279 is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0); in xilinx_gpio_of_to_plat()
281 plat->bank_max[1] = dev_read_u32_default(dev, in xilinx_gpio_of_to_plat()
283 plat->bank_input[1] = dev_read_u32_default(dev, in xilinx_gpio_of_to_plat()
285 plat->bank_output[1] = dev_read_u32_default(dev, in xilinx_gpio_of_to_plat()
287 plat->dout_default[1] = dev_read_u32_default(dev, in xilinx_gpio_of_to_plat()
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| A D | hsdk-creg-gpio.c | 87 gpio_count = dev_read_u32_default(dev, "gpio-count", 1); in hsdk_creg_gpio_probe()
88 shift = dev_read_u32_default(dev, "gpio-first-shift", 0); in hsdk_creg_gpio_probe()
89 bit_per_gpio = dev_read_u32_default(dev, "gpio-bit-per-line", 1); in hsdk_creg_gpio_probe()
90 activate = dev_read_u32_default(dev, "gpio-activate-val", 1); in hsdk_creg_gpio_probe()
91 deactivate = dev_read_u32_default(dev, "gpio-deactivate-val", 0); in hsdk_creg_gpio_probe()
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| A D | mscc_sgpio.c | 214 priv->ports = dev_read_u32_default(dev, "mscc,sgpio-ports", 0xFFFFFFFF); in mscc_sgpio_probe()
215 priv->clock = dev_read_u32_default(dev, "mscc,sgpio-frequency", in mscc_sgpio_probe()
223 uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", in mscc_sgpio_probe()
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| /u-boot/drivers/sysreset/ |
| A D | poweroff_gpio.c | 69 priv->active_delay_ms = dev_read_u32_default(dev, "active-delay-ms", 100); in poweroff_gpio_probe()
70 priv->inactive_delay_ms = dev_read_u32_default(dev, "inactive-delay-ms", 100); in poweroff_gpio_probe()
71 priv->timeout_ms = dev_read_u32_default(dev, "timeout-ms", 3000); in poweroff_gpio_probe()
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| /u-boot/drivers/power/regulator/ |
| A D | regulator_common.c | 39 dev_pdata->startup_delay_us = dev_read_u32_default(dev, in regulator_common_of_to_plat()
42 dev_read_u32_default(dev, "off-on-delay-us", 0); in regulator_common_of_to_plat()
45 dev_read_u32_default(dev, "u-boot,off-on-delay-us", 0); in regulator_common_of_to_plat()
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| A D | regulator-uclass.c | 432 uc_pdata->min_uV = dev_read_u32_default(dev, "regulator-min-microvolt", in regulator_pre_probe()
434 uc_pdata->max_uV = dev_read_u32_default(dev, "regulator-max-microvolt", in regulator_pre_probe()
436 uc_pdata->init_uV = dev_read_u32_default(dev, "regulator-init-microvolt", in regulator_pre_probe()
438 uc_pdata->min_uA = dev_read_u32_default(dev, "regulator-min-microamp", in regulator_pre_probe()
440 uc_pdata->max_uA = dev_read_u32_default(dev, "regulator-max-microamp", in regulator_pre_probe()
444 uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay", in regulator_pre_probe()
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| /u-boot/drivers/reset/ |
| A D | reset-syscon.c | 62 priv->offset = dev_read_u32_default(dev, "offset", 0); in syscon_reset_probe()
63 priv->mask = dev_read_u32_default(dev, "mask", 0); in syscon_reset_probe()
64 priv->assert_high = dev_read_u32_default(dev, "assert-high", true); in syscon_reset_probe()
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| /u-boot/drivers/clk/ |
| A D | clk_fixed_factor.c | 51 ff->div = dev_read_u32_default(dev, "clock-div", 1); in clk_fixed_factor_of_to_plat()
52 ff->mult = dev_read_u32_default(dev, "clock-mult", 1); in clk_fixed_factor_of_to_plat()
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| A D | clk_fixed_rate.c | 33 dev_read_u32_default(dev, "clock-frequency", 0); in clk_fixed_rate_of_to_plat()
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| /u-boot/drivers/watchdog/ |
| A D | wdt-uclass.c | 46 timeout = dev_read_u32_default(gd->watchdog_dev, "timeout-sec", in initr_watchdog()
48 reset_period = dev_read_u32_default(gd->watchdog_dev, in initr_watchdog()
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| /u-boot/drivers/spi/ |
| A D | spi-uclass.c | 181 spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); in spi_post_probe()
451 plat->cs = dev_read_u32_default(dev, "reg", -1); in spi_slave_of_to_plat()
452 plat->max_hz = dev_read_u32_default(dev, "spi-max-frequency", in spi_slave_of_to_plat()
466 value = dev_read_u32_default(dev, "spi-tx-bus-width", 1); in spi_slave_of_to_plat()
484 value = dev_read_u32_default(dev, "spi-rx-bus-width", 1); in spi_slave_of_to_plat()
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| A D | cadence_qspi.c | 294 plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128); in cadence_spi_of_to_plat()
295 plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4); in cadence_spi_of_to_plat()
296 plat->trigger_address = dev_read_u32_default(bus, in cadence_spi_of_to_plat()
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| /u-boot/drivers/serial/ |
| A D | serial_omap.c | 116 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); in omap_serial_of_to_plat()
130 plat->clock = dev_read_u32_default(dev, "clock-frequency", in omap_serial_of_to_plat()
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| /u-boot/drivers/pinctrl/ |
| A D | pinctrl-single.c | 159 dev_read_u32_default(dev, "pinctrl-single,register-width", 0); in single_of_to_plat()
173 pdata->mask = dev_read_u32_default(dev, "pinctrl-single,function-mask", in single_of_to_plat()
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| /u-boot/drivers/remoteproc/ |
| A D | ti_k3_arm64_rproc.c | 144 tsp->proc_id = dev_read_u32_default(dev, "ti,sci-proc-id", INVALID_ID); in ti_sci_proc_of_to_priv()
149 tsp->host_id = dev_read_u32_default(dev, "ti,sci-host-id", INVALID_ID); in ti_sci_proc_of_to_priv()
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| /u-boot/drivers/input/ |
| A D | cros_ec_keyb.c | 188 config->key_rows = dev_read_u32_default(dev, "keypad,num-rows", 0); in cros_ec_keyb_decode_fdt()
189 config->key_cols = dev_read_u32_default(dev, "keypad,num-columns", 0); in cros_ec_keyb_decode_fdt()
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| /u-boot/drivers/bootcount/ |
| A D | i2c-eeprom.c | 74 priv->offset = dev_read_u32_default(dev, "offset", 0); in bootcount_i2c_eeprom_probe()
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