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Searched refs:dram_cfg_param (Results 1 – 22 of 22) sorted by relevance

/u-boot/board/gateworks/venice/
A Dlpddr4_timing.c13 static struct dram_cfg_param lpddr4_ddrc_cfg_1gb[] = {
123 static struct dram_cfg_param lpddr4_ddrphy_cfg_1gb[] = {
1050 static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = {
1125 static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = {
1200 static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = {
1350 struct dram_cfg_param lpddr4_phy_pie[] = {
1991 static struct dram_cfg_param lpddr4_ddrc_cfg_4gb[] = {
2101 static struct dram_cfg_param lpddr4_ddrphy_cfg_4gb[] = {
2305 static struct dram_cfg_param lpddr4_fsp0_cfg_4gb[] = {
2343 static struct dram_cfg_param lpddr4_fsp1_cfg_4gb[] = {
[all …]
/u-boot/board/freescale/imx8mn_evk/
A Dddr4_timing.c13 struct dram_cfg_param ddr_ddrc_cfg[] = {
132 struct dram_cfg_param ddr_ddrphy_cfg[] = {
267 struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
794 struct dram_cfg_param ddr_fsp0_cfg[] = {
838 struct dram_cfg_param ddr_fsp1_cfg[] = {
881 struct dram_cfg_param ddr_fsp2_cfg[] = {
924 struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
967 struct dram_cfg_param ddr_phy_pie[] = {
/u-boot/board/beacon/imx8mn/
A Dlpddr4_timing.c9 struct dram_cfg_param ddr_ddrc_cfg[] = {
119 struct dram_cfg_param ddr_ddrphy_cfg[] = {
273 struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
676 struct dram_cfg_param ddr_fsp0_cfg[] = {
713 struct dram_cfg_param ddr_fsp1_cfg[] = {
751 struct dram_cfg_param ddr_fsp2_cfg[] = {
789 struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
828 struct dram_cfg_param ddr_phy_pie[] = {
A Dlpddr4_2g_timing.c12 struct dram_cfg_param ddr_ddrc_cfg[] = {
122 struct dram_cfg_param ddr_ddrphy_cfg[] = {
276 struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
679 struct dram_cfg_param ddr_fsp0_cfg[] = {
716 struct dram_cfg_param ddr_fsp1_cfg[] = {
754 struct dram_cfg_param ddr_fsp2_cfg[] = {
792 struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
831 struct dram_cfg_param ddr_phy_pie[] = {
/u-boot/board/phytec/phycore_imx8mm/
A Dlpddr4_timing.c11 static struct dram_cfg_param ddr_ddrc_cfg[] = {
121 static struct dram_cfg_param ddr_ddrphy_cfg[] = {
325 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
1048 struct dram_cfg_param ddr_fsp0_cfg[] = {
1087 static struct dram_cfg_param ddr_fsp1_cfg[] = {
1127 static struct dram_cfg_param ddr_fsp2_cfg[] = {
1167 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1207 static struct dram_cfg_param ddr_phy_pie[] = {
/u-boot/board/phytec/phycore_imx8mp/
A Dlpddr4_timing.c11 static struct dram_cfg_param ddr_ddrc_cfg[] = {
121 static struct dram_cfg_param ddr_ddrphy_cfg[] = {
330 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
1053 static struct dram_cfg_param ddr_fsp0_cfg[] = {
1092 static struct dram_cfg_param ddr_fsp1_cfg[] = {
1132 static struct dram_cfg_param ddr_fsp2_cfg[] = {
1172 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1213 static struct dram_cfg_param ddr_phy_pie[] = {
/u-boot/board/freescale/imx8mp_evk/
A Dlpddr4_timing.c9 struct dram_cfg_param ddr_ddrc_cfg[] = {
120 struct dram_cfg_param ddr_ddrphy_cfg[] = {
329 struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
1052 struct dram_cfg_param ddr_fsp0_cfg[] = {
1091 struct dram_cfg_param ddr_fsp1_cfg[] = {
1131 struct dram_cfg_param ddr_fsp2_cfg[] = {
1171 struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1212 struct dram_cfg_param ddr_phy_pie[] = {
/u-boot/board/toradex/verdin-imx8mm/
A Dlpddr4_timing.c15 struct dram_cfg_param ddr_ddrc_cfg[] = {
125 struct dram_cfg_param ddr_ddrphy_cfg[] = {
329 struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
1052 struct dram_cfg_param ddr_fsp0_cfg[] = {
1091 struct dram_cfg_param ddr_fsp1_cfg[] = {
1131 struct dram_cfg_param ddr_fsp2_cfg[] = {
1171 struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1211 struct dram_cfg_param ddr_phy_pie[] = {
/u-boot/board/google/imx8mq_phanbell/
A Dlpddr4_timing_1g.c12 static struct dram_cfg_param ddr_ddrc_cfg[] = {
104 static struct dram_cfg_param ddr_ddrphy_cfg[] = {
269 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
992 static struct dram_cfg_param ddr_fsp0_cfg[] = {
1031 static struct dram_cfg_param ddr_fsp1_cfg[] = {
1071 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1111 static struct dram_cfg_param ddr_phy_pie[] = {
/u-boot/board/technexion/pico-imx8mq/
A Dlpddr4_timing_1gb.c14 static struct dram_cfg_param ddr_ddrc_cfg[] = {
106 static struct dram_cfg_param ddr_ddrphy_cfg[] = {
271 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
994 static struct dram_cfg_param ddr_fsp0_cfg[] = {
1033 static struct dram_cfg_param ddr_fsp1_cfg[] = {
1073 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1113 static struct dram_cfg_param ddr_phy_pie[] = {
A Dlpddr4_timing_2gb.c14 static struct dram_cfg_param ddr_ddrc_cfg[] = {
106 static struct dram_cfg_param ddr_ddrphy_cfg[] = {
271 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
994 static struct dram_cfg_param ddr_fsp0_cfg[] = {
1033 static struct dram_cfg_param ddr_fsp1_cfg[] = {
1073 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1113 static struct dram_cfg_param ddr_phy_pie[] = {
A Dlpddr4_timing_3gb.c14 static struct dram_cfg_param ddr_ddrc_cfg[] = {
106 static struct dram_cfg_param ddr_ddrphy_cfg[] = {
271 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
994 static struct dram_cfg_param ddr_fsp0_cfg[] = {
1033 static struct dram_cfg_param ddr_fsp1_cfg[] = {
1073 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1113 static struct dram_cfg_param ddr_phy_pie[] = {
A Dlpddr4_timing_4gb.c14 static struct dram_cfg_param ddr_ddrc_cfg[] = {
106 static struct dram_cfg_param ddr_ddrphy_cfg[] = {
271 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
994 static struct dram_cfg_param ddr_fsp0_cfg[] = {
1033 static struct dram_cfg_param ddr_fsp1_cfg[] = {
1073 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
1113 static struct dram_cfg_param ddr_phy_pie[] = {
/u-boot/board/beacon/imx8mm/
A Dlpddr4_timing.c11 struct dram_cfg_param lpddr4_ddrc_cfg[] = {
126 struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
323 struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
1046 struct dram_cfg_param lpddr4_fsp0_cfg[] = {
1121 struct dram_cfg_param lpddr4_fsp1_cfg[] = {
1196 struct dram_cfg_param lpddr4_fsp2_cfg[] = {
1271 struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
1346 struct dram_cfg_param lpddr4_phy_pie[] = {
/u-boot/board/freescale/imx8mm_evk/
A Dlpddr4_timing.c11 struct dram_cfg_param lpddr4_ddrc_cfg[] = {
126 struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
323 struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
1046 struct dram_cfg_param lpddr4_fsp0_cfg[] = {
1121 struct dram_cfg_param lpddr4_fsp1_cfg[] = {
1196 struct dram_cfg_param lpddr4_fsp2_cfg[] = {
1271 struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
1346 struct dram_cfg_param lpddr4_phy_pie[] = {
/u-boot/board/freescale/imx8mq_evk/
A Dlpddr4_timing_b0.c13 static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
136 static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
321 static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
399 static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
475 static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
554 static struct dram_cfg_param lpddr4_phy_pie[] = {
A Dlpddr4_timing.c13 struct dram_cfg_param lpddr4_ddrc_cfg[] = {
138 struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
332 struct dram_cfg_param lpddr4_fsp0_cfg[] = {
438 struct dram_cfg_param lpddr4_fsp1_cfg[] = {
520 struct dram_cfg_param lpddr4_fsp2_cfg[] = {
597 struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
691 struct dram_cfg_param lpddr4_phy_pie[] = {
/u-boot/drivers/ddr/imx/imx8m/
A Dddrphy_csr.c10 struct dram_cfg_param ddrphy_trained_csr[] = {
A Dhelper.c115 void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, in ddrphy_trained_csr_save()
137 struct dram_cfg_param *cfg; in dram_config_save()
148 cfg = (struct dram_cfg_param *)(saved_timing_base + in dram_config_save()
A Dddrphy_train.c15 struct dram_cfg_param *dram_cfg; in ddr_cfg_phy()
A Dddr_init.c14 void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) in ddr_cfg_umctl2()
/u-boot/arch/arm/include/asm/arch-imx8m/
A Dddr.h673 struct dram_cfg_param { struct
681 struct dram_cfg_param *fsp_cfg; argument
687 struct dram_cfg_param *ddrc_cfg;
690 struct dram_cfg_param *ddrphy_cfg;
696 struct dram_cfg_param *ddrphy_trained_csr;
699 struct dram_cfg_param *ddrphy_pie;
711 void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
747 extern struct dram_cfg_param ddrphy_trained_csr[];

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