Searched refs:emif_pwr_mgmt_ctrl (Results 1 – 3 of 3) sorted by relevance
33 reg = readl(&emif->emif_pwr_mgmt_ctrl); in set_lpmode_selfrefresh()37 writel(reg, &emif->emif_pwr_mgmt_ctrl); in set_lpmode_selfrefresh()40 readl(&emif->emif_pwr_mgmt_ctrl); in set_lpmode_selfrefresh()183 writel(0, &emif->emif_pwr_mgmt_ctrl); in emif_update_timings()185 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); in emif_update_timings()212 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); in omap5_ddr3_leveling()231 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); in omap5_ddr3_leveling()422 writel(0x0, &emif->emif_pwr_mgmt_ctrl); in dra7_ddr3_init()1326 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl); in emif_post_init_config()
91 writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); in config_sdram_emif4d5()
652 u32 emif_pwr_mgmt_ctrl; member
Completed in 14 milliseconds