| /u-boot/doc/device-tree-bindings/misc/ |
| A D | intel,baytrail-fsp.txt | 14 - fsp,enable-sdio
18 - fsp,enable-spi
19 - fsp,enable-sata
21 - fsp,enable-xhci
22 - fsp,enable-dma0
33 - fsp,enable-hsi
35 - fsp,isp-enable
57 - fsp,lpe-mode
61 - fsp,gtt-size
62 - fsp,scc-mode
[all …]
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| /u-boot/arch/x86/lib/fsp1/ |
| A D | fsp_support.c | 24 volatile register u8 *fsp asm("eax"); in fsp_find_header()
27 fsp = (u8 *)CONFIG_FSP_ADDR; in fsp_find_header()
32 fsp += ((struct fv_header *)fsp)->ext_hdr_off; in fsp_find_header()
33 fsp += ((struct fv_ext_header *)fsp)->ext_hdr_size; in fsp_find_header()
34 fsp = (u8 *)(((u32)fsp + 7) & 0xFFFFFFF8); in fsp_find_header()
36 fsp = 0; in fsp_find_header()
40 if (fsp && in fsp_find_header()
60 fsp = 0; in fsp_find_header()
63 if (fsp && in fsp_find_header()
68 fsp = 0; in fsp_find_header()
[all …]
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| /u-boot/arch/x86/dts/ |
| A D | cherryhill.dts | 163 fsp {
165 fsp,memory-upd {
174 fsp,enable-dvfs;
177 fsp,silicon-upd {
181 fsp,enable-sata;
182 fsp,enable-xhci;
184 fsp,enable-dma0;
185 fsp,enable-dma1;
186 fsp,enable-i2c0;
187 fsp,enable-i2c1;
[all …]
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| A D | dfi-bt700.dtsi | 261 fsp {
268 fsp,enable-sdio;
272 fsp,enable-spi;
273 fsp,enable-sata;
276 fsp,enable-xhci;
280 fsp,enable-dma0;
281 fsp,enable-dma1;
282 fsp,enable-i2c0;
283 fsp,enable-i2c1;
284 fsp,enable-i2c2;
[all …]
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| A D | minnowmax.dts | 263 fsp {
270 fsp,enable-sdio;
273 fsp,enable-spi;
274 fsp,enable-sata;
277 fsp,enable-xhci;
281 fsp,enable-dma0;
282 fsp,enable-dma1;
283 fsp,enable-i2c0;
284 fsp,enable-i2c1;
285 fsp,enable-i2c2;
[all …]
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| A D | conga-qeval20-qa3-e3845.dts | 250 fsp {
257 fsp,enable-sdio;
258 fsp,enable-sdcard;
260 fsp,enable-spi;
261 fsp,enable-sata;
264 fsp,enable-xhci;
268 fsp,enable-dma0;
269 fsp,enable-dma1;
270 fsp,enable-pwm0;
271 fsp,enable-pwm1;
[all …]
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| A D | bayleybay.dts | 239 fsp {
246 fsp,enable-sdio;
249 fsp,enable-spi;
250 fsp,enable-sata;
254 fsp,enable-dma0;
255 fsp,enable-dma1;
256 fsp,enable-i2c0;
257 fsp,enable-i2c1;
258 fsp,enable-i2c2;
259 fsp,enable-i2c3;
[all …]
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| A D | baytrail_som-db5800-som-6867.dts | 263 fsp {
269 fsp,enable-spi;
270 fsp,enable-sata;
274 fsp,enable-dma0;
275 fsp,enable-dma1;
276 fsp,enable-i2c0;
277 fsp,enable-i2c1;
278 fsp,enable-i2c2;
279 fsp,enable-i2c3;
280 fsp,enable-i2c4;
[all …]
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| A D | u-boot.dtsi | 106 intel-fsp {
134 intel-fsp-m {
137 intel-fsp-s {
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| A D | cougarcanyon2.dts | 86 fsp {
87 compatible = "intel,ivybridge-fsp";
88 fsp,enable-ht;
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| /u-boot/arch/x86/lib/fsp2/ |
| A D | fsp_support.c | 23 struct fsp_header *fsp; in fsp_get_header() local
82 fsp = ptr; in fsp_get_header()
85 log_debug("fsp %x, fsp-buf=%x, si=%x\n", (uint)fsp, ptr - (void *)buf, in fsp_get_header()
86 (void *)&fsp->fsp_silicon_init - (void *)buf); in fsp_get_header()
87 if (fsp->sign != EFI_FSPH_SIGNATURE) in fsp_get_header()
90 base = (void *)fsp->img_base; in fsp_get_header()
92 if (fsp->fsp_mem_init) in fsp_get_header()
93 log_debug("mem_init offset %x\n", (uint)fsp->fsp_mem_init); in fsp_get_header()
94 else if (fsp->fsp_silicon_init) in fsp_get_header()
96 (uint)fsp->fsp_silicon_init); in fsp_get_header()
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| /u-boot/tools/binman/test/ |
| A D | 042_intel_fsp.dts | 10 intel-fsp {
11 filename = "fsp.bin";
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| A D | 152_intel_fsp_m.dts | 10 intel-fsp-m {
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| A D | 153_intel_fsp_s.dts | 10 intel-fsp-s {
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| A D | 154_intel_fsp_t.dts | 10 intel-fsp-t {
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| /u-boot/drivers/ddr/imx/imx8m/ |
| A D | ddrphy_utils.c | 216 void get_trained_CDD(u32 fsp) in get_trained_CDD() argument
251 g_cdd_rr_max[fsp] = cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max; in get_trained_CDD()
252 g_cdd_rw_max[fsp] = cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max; in get_trained_CDD()
253 g_cdd_wr_max[fsp] = cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max; in get_trained_CDD()
254 g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max; in get_trained_CDD()
264 g_cdd_rr_max[fsp] = look_for_max(ddr4_cdd, 1, 12); in get_trained_CDD()
265 g_cdd_ww_max[fsp] = look_for_max(ddr4_cdd, 13, 24); in get_trained_CDD()
266 g_cdd_rw_max[fsp] = look_for_max(ddr4_cdd, 25, 40); in get_trained_CDD()
267 g_cdd_wr_max[fsp] = look_for_max(ddr4_cdd, 41, 56); in get_trained_CDD()
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| /u-boot/doc/board/intel/ |
| A D | minnowmax.rst | 10 it to fsp.bin.
45 69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin
61 7c0000 fsp.bin CONFIG_FSP_ADDR
62 7f8000 <spare> (depends on size of fsp.bin)
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| A D | crownbay.rst | 21 Rename the first one to fsp.bin and second one to cmc.bin and put them in the
41 .. _`FSP`: http://www.intel.com/fsp
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| A D | bayleybay.rst | 10 it to fsp.bin.
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| A D | cougarcanyon2.rst | 10 time of writing) in the board directory and rename it to fsp.bin.
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| A D | cherryhill.rst | 8 put the .fd file to the board directory and rename it to fsp.bin.
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| /u-boot/cmd/x86/ |
| A D | Makefile | 6 obj-$(CONFIG_HAVE_FSP) += fsp.o
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| A D | fsp.c | 107 fsp, 2, 1, do_fsp,
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| /u-boot/arch/x86/lib/fsp/ |
| A D | fsp_dram.c | 45 efi_guid_t fsp = FSP_HOB_RESOURCE_OWNER_FSP_GUID; in dram_init_banksize() local
68 if (!guidcmp(&res_desc->owner, &fsp)) in dram_init_banksize()
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| /u-boot/drivers/pinctrl/intel/ |
| A D | Kconfig | 35 property in the host bridge and the pads property in the fsp-s
|