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Searched refs:gate (Results 1 – 25 of 87) sorted by relevance

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/u-boot/drivers/clk/
A Dclk-gate.c61 reg = gate->io_gate_val; in clk_gate_endisable()
63 reg = readl(gate->reg); in clk_gate_endisable()
72 writel(reg, gate->reg); in clk_gate_endisable()
95 reg = gate->io_gate_val; in clk_gate_is_enabled()
97 reg = readl(gate->reg); in clk_gate_is_enabled()
120 struct clk_gate *gate; in clk_register_gate() local
132 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in clk_register_gate()
133 if (!gate) in clk_register_gate()
137 gate->reg = reg; in clk_register_gate()
144 clk = &gate->clk; in clk_register_gate()
[all …]
A Dclk_sandbox_ccf.c99 gate->state = 1; in clk_gate2_enable()
107 gate->state = 0; in clk_gate2_disable()
127 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in sandbox_clk_register_gate2()
128 if (!gate) in sandbox_clk_register_gate2()
131 gate->state = 0; in sandbox_clk_register_gate2()
132 clk = &gate->clk; in sandbox_clk_register_gate2()
137 kfree(gate); in sandbox_clk_register_gate2()
199 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in sandbox_clk_composite()
200 if (!gate) in sandbox_clk_composite()
203 gate->reg = reg; in sandbox_clk_composite()
[all …]
A Dclk-composite.c77 struct clk *gate = composite->gate; in clk_composite_enable() local
79 if (gate && gate_ops) in clk_composite_enable()
80 return gate_ops->enable(gate); in clk_composite_enable()
90 struct clk *gate = composite->gate; in clk_composite_disable() local
92 if (gate && gate_ops) in clk_composite_disable()
93 return gate_ops->disable(gate); in clk_composite_disable()
104 struct clk *gate, in clk_register_composite() argument
136 if (gate && gate_ops) { in clk_register_composite()
142 composite->gate = gate; in clk_register_composite()
144 gate->data = (ulong)composite; in clk_register_composite()
[all …]
/u-boot/drivers/clk/imx/
A Dclk-gate2.c45 reg = readl(gate->reg); in clk_gate2_enable()
47 reg |= gate->cgr_val << gate->bit_idx; in clk_gate2_enable()
48 writel(reg, gate->reg); in clk_gate2_enable()
58 reg = readl(gate->reg); in clk_gate2_disable()
60 writel(reg, gate->reg); in clk_gate2_disable()
87 struct clk_gate2 *gate; in clk_register_gate2() local
91 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in clk_register_gate2()
92 if (!gate) in clk_register_gate2()
95 gate->reg = reg; in clk_register_gate2()
100 clk = &gate->clk; in clk_register_gate2()
[all …]
A Dclk-composite-8m.c127 struct clk_gate *gate = NULL; in imx8m_clk_composite_flags() local
150 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in imx8m_clk_composite_flags()
151 if (!gate) in imx8m_clk_composite_flags()
154 gate->reg = reg; in imx8m_clk_composite_flags()
155 gate->bit_idx = PCG_CGC_SHIFT; in imx8m_clk_composite_flags()
156 gate->flags = flags; in imx8m_clk_composite_flags()
162 &gate->clk, &clk_gate_ops, flags); in imx8m_clk_composite_flags()
169 kfree(gate); in imx8m_clk_composite_flags()
/u-boot/drivers/clk/sunxi/
A Dclk_sunxi.c27 const struct ccu_clk_gate *gate = priv_to_gate(priv, clk->id); in sunxi_set_gate() local
30 if (!(gate->flags & CCU_CLK_F_IS_VALID)) { in sunxi_set_gate()
36 clk->id, gate->off, ilog2(gate->bit)); in sunxi_set_gate()
38 reg = readl(priv->base + gate->off); in sunxi_set_gate()
40 reg |= gate->bit; in sunxi_set_gate()
42 reg &= ~gate->bit; in sunxi_set_gate()
44 writel(reg, priv->base + gate->off); in sunxi_set_gate()
/u-boot/drivers/clk/meson/
A Dg12a-ao.c29 struct meson_gate *gate; in meson_set_gate() local
34 gate = &gates[clk->id]; in meson_set_gate()
36 if (gate->reg == 0) in meson_set_gate()
39 regmap_update_bits(priv->map, gate->reg, in meson_set_gate()
40 BIT(gate->bit), on ? BIT(gate->bit) : 0); in meson_set_gate()
/u-boot/doc/device-tree-bindings/clock/
A Drockchip.txt12 The gate registers form a continuos block which makes the dt node
14 one gate clock spanning all registers or they can be divided into
19 - compatible : "rockchip,rk2928-gate-clk"
22 - clock-output-names : the corresponding gate names that the clock controls
23 - clocks : should contain the parent clock for each individual gate,
27 Example using multiple gate clocks:
29 clk_gates0: gate-clk@200000d0 {
30 compatible = "rockchip,rk2928-gate-clk";
54 clk_gates1: gate-clk@200000d4 {
55 compatible = "rockchip,rk2928-gate-clk";
/u-boot/arch/arm/dts/
A Dsocfpga.dtsi305 clk-gate = <0x60 0>;
320 clk-gate = <0x60 1>;
335 clk-gate = <0x60 2>;
343 clk-gate = <0x60 3>;
351 clk-gate = <0x60 4>;
359 clk-gate = <0x60 5>;
367 clk-gate = <0x60 6>;
374 clk-gate = <0x60 7>;
381 clk-gate = <0x60 8>;
388 clk-gate = <0x60 9>;
[all …]
A Dam35xx-clocks.dtsi13 compatible = "ti,am35xx-gate-clock";
21 compatible = "ti,gate-clock";
29 compatible = "ti,am35xx-gate-clock";
37 compatible = "ti,gate-clock";
45 compatible = "ti,am35xx-gate-clock";
53 compatible = "ti,gate-clock";
61 compatible = "ti,am35xx-gate-clock";
98 compatible = "ti,wait-gate-clock";
A Domap36xx-clocks.dtsi20 compatible = "ti,hsdiv-gate-clock";
30 compatible = "ti,hsdiv-gate-clock";
39 compatible = "ti,hsdiv-gate-clock";
48 compatible = "ti,hsdiv-gate-clock";
57 compatible = "ti,hsdiv-gate-clock";
66 compatible = "ti,wait-gate-clock";
A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi48 compatible = "ti,composite-gate-clock";
109 compatible = "ti,wait-gate-clock";
117 compatible = "ti,gate-clock";
125 compatible = "ti,gate-clock";
133 compatible = "ti,wait-gate-clock";
157 compatible = "ti,wait-gate-clock";
165 compatible = "ti,dss-gate-clock";
182 compatible = "ti,gate-clock";
190 compatible = "ti,dss-gate-clock";
A Domap3xxx-clocks.dtsi36 compatible = "ti,gate-clock";
222 compatible = "ti,gate-clock";
264 compatible = "ti,gate-clock";
379 compatible = "ti,gate-clock";
438 compatible = "ti,gate-clock";
466 compatible = "ti,gate-clock";
494 compatible = "ti,gate-clock";
943 compatible = "ti,gate-clock";
951 compatible = "ti,gate-clock";
959 compatible = "ti,gate-clock";
[all …]
A Dam43xx-clocks.dtsi109 compatible = "ti,gate-clock";
117 compatible = "ti,gate-clock";
125 compatible = "ti,gate-clock";
133 compatible = "ti,gate-clock";
141 compatible = "ti,gate-clock";
149 compatible = "ti,gate-clock";
351 compatible = "ti,gate-clock";
504 compatible = "ti,gate-clock";
512 compatible = "ti,gate-clock";
520 compatible = "ti,gate-clock";
[all …]
A Dsocfpga_arria10.dtsi329 clk-gate = <0x48 1>;
337 clk-gate = <0x48 2>;
345 clk-gate = <0x48 3>;
353 clk-gate = <0x48 0>;
360 clk-gate = <0xC8 5>;
368 clk-gate = <0xC8 11>;
375 clk-gate = <0xC8 10>;
382 clk-gate = <0xC8 10>;
397 clk-gate = <0xC8 9>;
404 clk-gate = <0xC8 8>;
[all …]
/u-boot/arch/arm/cpu/armv7/bcm235xx/
A Dclk-core.h96 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) argument
97 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) argument
98 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) argument
99 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) argument
100 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) argument
101 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) argument
103 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) argument
391 struct bcm_clk_gate gate; member
395 struct bcm_clk_gate gate; member
399 struct bcm_clk_gate gate; member
A Dclk-bcm235xx.c144 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
156 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
168 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
180 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
193 .gate = SW_ONLY_GATE(0x0358, 20, 4),
198 .gate = SW_ONLY_GATE(0x035c, 20, 4),
203 .gate = SW_ONLY_GATE(0x0364, 20, 4),
208 .gate = SW_ONLY_GATE(0x0360, 20, 4),
233 .gate = HW_SW_GATE(0x0458, 18, 2, 3),
244 .gate = HW_SW_GATE(0x045c, 18, 2, 3),
[all …]
A Dclk-core.c85 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable() local
107 if (gate_exists(gate)) { in peri_clk_enable()
109 reg |= (1 << cd->gate.en_bit); in peri_clk_enable()
140 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); in peri_clk_enable()
147 reg = readl(base + cd->gate.offset); in peri_clk_enable()
148 reg &= ~(1 << cd->gate.en_bit); in peri_clk_enable()
149 writel(reg, base + cd->gate.offset); in peri_clk_enable()
152 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); in peri_clk_enable()
358 reg |= (1 << cd->gate.en_bit); in bus_clk_enable()
360 reg &= ~(1 << cd->gate.en_bit); in bus_clk_enable()
[all …]
/u-boot/arch/arm/cpu/armv7/bcm281xx/
A Dclk-core.h96 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) argument
97 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) argument
98 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) argument
99 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) argument
100 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) argument
101 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) argument
103 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) argument
391 struct bcm_clk_gate gate; member
395 struct bcm_clk_gate gate; member
399 struct bcm_clk_gate gate; member
A Dclk-bcm281xx.c144 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
156 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
168 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
180 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
193 .gate = SW_ONLY_GATE(0x0358, 20, 4),
198 .gate = SW_ONLY_GATE(0x035c, 20, 4),
203 .gate = SW_ONLY_GATE(0x0364, 20, 4),
208 .gate = SW_ONLY_GATE(0x0360, 20, 4),
233 .gate = HW_SW_GATE(0x0458, 18, 2, 3),
244 .gate = HW_SW_GATE(0x045c, 18, 2, 3),
[all …]
A Dclk-core.c85 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable() local
107 if (gate_exists(gate)) { in peri_clk_enable()
109 reg |= (1 << cd->gate.en_bit); in peri_clk_enable()
140 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); in peri_clk_enable()
147 reg = readl(base + cd->gate.offset); in peri_clk_enable()
148 reg &= ~(1 << cd->gate.en_bit); in peri_clk_enable()
149 writel(reg, base + cd->gate.offset); in peri_clk_enable()
152 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); in peri_clk_enable()
358 reg |= (1 << cd->gate.en_bit); in bus_clk_enable()
360 reg &= ~(1 << cd->gate.en_bit); in bus_clk_enable()
[all …]
/u-boot/drivers/clk/mediatek/
A Dclk-mtk.c419 u32 bit = BIT(gate->shift); in mtk_clk_gate_enable()
421 switch (gate->flags & CLK_GATE_MASK) { in mtk_clk_gate_enable()
423 writel(bit, priv->base + gate->regs->clr_ofs); in mtk_clk_gate_enable()
426 writel(bit, priv->base + gate->regs->set_ofs); in mtk_clk_gate_enable()
446 u32 bit = BIT(gate->shift); in mtk_clk_gate_disable()
448 switch (gate->flags & CLK_GATE_MASK) { in mtk_clk_gate_disable()
450 writel(bit, priv->base + gate->regs->set_ofs); in mtk_clk_gate_disable()
453 writel(bit, priv->base + gate->regs->clr_ofs); in mtk_clk_gate_disable()
474 switch (gate->flags & CLK_PARENT_MASK) { in mtk_clk_gate_get_rate()
476 return mtk_clk_find_parent_rate(clk, gate->parent, in mtk_clk_gate_get_rate()
[all …]
/u-boot/arch/arm/mach-imx/mx7ulp/
A Dscg.c171 u32 shift, mask, gate, valid; in scg_apll_pfd_get_rate() local
175 gate = SCG_PLL_PFD0_GATE_MASK; in scg_apll_pfd_get_rate()
181 gate = SCG_PLL_PFD1_GATE_MASK; in scg_apll_pfd_get_rate()
187 gate = SCG_PLL_PFD2_GATE_MASK; in scg_apll_pfd_get_rate()
193 gate = SCG_PLL_PFD3_GATE_MASK; in scg_apll_pfd_get_rate()
221 u32 shift, mask, gate, valid; in scg_spll_pfd_get_rate() local
225 gate = SCG_PLL_PFD0_GATE_MASK; in scg_spll_pfd_get_rate()
231 gate = SCG_PLL_PFD1_GATE_MASK; in scg_spll_pfd_get_rate()
634 u32 shift, mask, gate, valid; in scg_enable_pll_pfd() local
695 reg |= gate; in scg_enable_pll_pfd()
[all …]
/u-boot/arch/arm/mach-imx/
A Drdc-sema.c66 &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_lock()
67 reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_lock()
94 reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_unlock()
98 writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_unlock()
/u-boot/drivers/clk/kendryte/
A Dclk.c330 u8 gate; member
338 .gate = (_gate), \
391 struct clk_gate *gate = kzalloc(sizeof(*gate), GFP_KERNEL); in k210_create_gate() local
393 if (!gate) in k210_create_gate()
394 return gate; in k210_create_gate()
396 gate->reg = base + params->off; in k210_create_gate()
399 return gate; in k210_create_gate()
429 struct clk_gate *gate; in k210_register_comp() local
455 gate = k210_create_gate(&k210_gates[params->gate], base); in k210_register_comp()
456 if (!gate) { in k210_register_comp()
[all …]

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