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/u-boot/drivers/net/phy/
A Dmv88e61xx.c200 u8 global1; /* Offset of Switch Global 1 registers */ member
559 val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_CTRL); in mv88e61xx_switch_reset()
563 val = mv88e61xx_reg_write(phydev, priv->global1, in mv88e61xx_switch_reset()
570 val = mv88e61xx_reg_read(phydev, priv->global1, in mv88e61xx_switch_reset()
767 val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_MON_CTRL); in mv88e61xx_set_cpu_port()
773 val = mv88e61xx_reg_write(phydev, priv->global1, in mv88e61xx_set_cpu_port()
910 priv->global1 = 0x1B; in mv88e61xx_priv_reg_offs_pre_init()
922 priv->global1 = 0x0F; in mv88e61xx_priv_reg_offs_pre_init()

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