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Searched refs:hz (Results 1 – 25 of 89) sorted by relevance

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/u-boot/arch/arm/dts/
A Dmeson-g12b-a311d.dtsi15 opp-hz = /bits/ 64 <100000000>;
20 opp-hz = /bits/ 64 <250000000>;
25 opp-hz = /bits/ 64 <500000000>;
30 opp-hz = /bits/ 64 <667000000>;
35 opp-hz = /bits/ 64 <1000000000>;
40 opp-hz = /bits/ 64 <1200000000>;
45 opp-hz = /bits/ 64 <1398000000>;
50 opp-hz = /bits/ 64 <1512000000>;
55 opp-hz = /bits/ 64 <1608000000>;
75 opp-hz = /bits/ 64 <100000000>;
[all …]
A Dmeson-g12b-s922x.dtsi15 opp-hz = /bits/ 64 <100000000>;
20 opp-hz = /bits/ 64 <250000000>;
25 opp-hz = /bits/ 64 <500000000>;
30 opp-hz = /bits/ 64 <667000000>;
35 opp-hz = /bits/ 64 <1000000000>;
40 opp-hz = /bits/ 64 <1200000000>;
45 opp-hz = /bits/ 64 <1398000000>;
50 opp-hz = /bits/ 64 <1512000000>;
55 opp-hz = /bits/ 64 <1608000000>;
80 opp-hz = /bits/ 64 <100000000>;
[all …]
A Drk3399-op1-opp.dtsi12 opp-hz = /bits/ 64 <408000000>;
17 opp-hz = /bits/ 64 <600000000>;
21 opp-hz = /bits/ 64 <816000000>;
25 opp-hz = /bits/ 64 <1008000000>;
29 opp-hz = /bits/ 64 <1200000000>;
33 opp-hz = /bits/ 64 <1416000000>;
37 opp-hz = /bits/ 64 <1512000000>;
47 opp-hz = /bits/ 64 <408000000>;
52 opp-hz = /bits/ 64 <600000000>;
56 opp-hz = /bits/ 64 <816000000>;
[all …]
A Drk3399-opp.dtsi12 opp-hz = /bits/ 64 <408000000>;
17 opp-hz = /bits/ 64 <600000000>;
21 opp-hz = /bits/ 64 <816000000>;
25 opp-hz = /bits/ 64 <1008000000>;
29 opp-hz = /bits/ 64 <1200000000>;
33 opp-hz = /bits/ 64 <1416000000>;
43 opp-hz = /bits/ 64 <408000000>;
48 opp-hz = /bits/ 64 <600000000>;
52 opp-hz = /bits/ 64 <816000000>;
56 opp-hz = /bits/ 64 <1008000000>;
[all …]
A Dsun50i-a64-cpu-opp.dtsi12 opp-hz = /bits/ 64 <648000000>;
18 opp-hz = /bits/ 64 <816000000>;
24 opp-hz = /bits/ 64 <912000000>;
30 opp-hz = /bits/ 64 <960000000>;
36 opp-hz = /bits/ 64 <1008000000>;
42 opp-hz = /bits/ 64 <1056000000>;
48 opp-hz = /bits/ 64 <1104000000>;
54 opp-hz = /bits/ 64 <1152000000>;
A Dmeson-g12a.dtsi61 opp-hz = /bits/ 64 <100000000>;
66 opp-hz = /bits/ 64 <250000000>;
71 opp-hz = /bits/ 64 <500000000>;
76 opp-hz = /bits/ 64 <666666666>;
81 opp-hz = /bits/ 64 <1000000000>;
86 opp-hz = /bits/ 64 <1200000000>;
91 opp-hz = /bits/ 64 <1398000000>;
96 opp-hz = /bits/ 64 <1512000000>;
101 opp-hz = /bits/ 64 <1608000000>;
106 opp-hz = /bits/ 64 <1704000000>;
[all …]
A Dmeson-gx-mali450.dtsi12 opp-hz = /bits/ 64 <125000000>;
16 opp-hz = /bits/ 64 <250000000>;
20 opp-hz = /bits/ 64 <285714285>;
24 opp-hz = /bits/ 64 <400000000>;
28 opp-hz = /bits/ 64 <500000000>;
32 opp-hz = /bits/ 64 <666666666>;
36 opp-hz = /bits/ 64 <744000000>;
A Dsun50i-h6-cpu-opp.dtsi13 opp-hz = /bits/ 64 <480000000>;
22 opp-hz = /bits/ 64 <720000000>;
31 opp-hz = /bits/ 64 <816000000>;
40 opp-hz = /bits/ 64 <888000000>;
49 opp-hz = /bits/ 64 <1080000000>;
58 opp-hz = /bits/ 64 <1320000000>;
67 opp-hz = /bits/ 64 <1488000000>;
76 opp-hz = /bits/ 64 <1608000000>;
85 opp-hz = /bits/ 64 <1704000000>;
94 opp-hz = /bits/ 64 <1800000000>;
A Dmeson-gxm.dtsi90 opp-hz = /bits/ 64 <125000000>;
94 opp-hz = /bits/ 64 <250000000>;
98 opp-hz = /bits/ 64 <285714285>;
102 opp-hz = /bits/ 64 <400000000>;
106 opp-hz = /bits/ 64 <500000000>;
110 opp-hz = /bits/ 64 <666666666>;
A Dsun8i-a33.dtsi54 opp-hz = /bits/ 64 <120000000>;
60 opp-hz = /bits/ 64 <240000000>;
66 opp-hz = /bits/ 64 <312000000>;
72 opp-hz = /bits/ 64 <408000000>;
78 opp-hz = /bits/ 64 <480000000>;
84 opp-hz = /bits/ 64 <504000000>;
90 opp-hz = /bits/ 64 <600000000>;
96 opp-hz = /bits/ 64 <648000000>;
102 opp-hz = /bits/ 64 <720000000>;
108 opp-hz = /bits/ 64 <816000000>;
[all …]
A Duniphier-pro5.dtsi43 opp-hz = /bits/ 64 <100000000>;
47 opp-hz = /bits/ 64 <116667000>;
51 opp-hz = /bits/ 64 <150000000>;
55 opp-hz = /bits/ 64 <175000000>;
59 opp-hz = /bits/ 64 <200000000>;
63 opp-hz = /bits/ 64 <233334000>;
67 opp-hz = /bits/ 64 <300000000>;
71 opp-hz = /bits/ 64 <350000000>;
75 opp-hz = /bits/ 64 <400000000>;
79 opp-hz = /bits/ 64 <466667000>;
[all …]
A Dimx8mm-evk.dts27 opp-hz = /bits/ 64 <25000000>;
31 opp-hz = /bits/ 64 <100000000>;
35 opp-hz = /bits/ 64 <750000000>;
A Dmeson-sm1.dtsi99 opp-hz = /bits/ 64 <100000000>;
104 opp-hz = /bits/ 64 <250000000>;
109 opp-hz = /bits/ 64 <500000000>;
114 opp-hz = /bits/ 64 <666666666>;
119 opp-hz = /bits/ 64 <1000000000>;
124 opp-hz = /bits/ 64 <1200000000>;
129 opp-hz = /bits/ 64 <1404000000>;
134 opp-hz = /bits/ 64 <1500000000>;
139 opp-hz = /bits/ 64 <1608000000>;
144 opp-hz = /bits/ 64 <1704000000>;
[all …]
A Drk3399-puma.dtsi35 opp-hz = /bits/ 64 <408000000>;
40 opp-hz = /bits/ 64 <600000000>;
44 opp-hz = /bits/ 64 <816000000>;
49 opp-hz = /bits/ 64 <1008000000>;
53 opp-hz = /bits/ 64 <1200000000>;
57 opp-hz = /bits/ 64 <1416000000>;
61 opp-hz = /bits/ 64 <1608000000>;
65 opp-hz = /bits/ 64 <1800000000>;
69 opp-hz = /bits/ 64 <1992000000>;
/u-boot/drivers/spi/
A Dcadence_qspi.c34 plat->ref_clk_hz, hz); in cadence_spi_write_speed()
55 static int spi_calibration(struct udevice *bus, uint hz) in spi_calibration() argument
79 cadence_spi_write_speed(bus, hz); in spi_calibration()
125 priv->qspi_calibrated_hz = hz; in spi_calibration()
137 if (hz > plat->max_hz) in cadence_spi_set_speed()
138 hz = plat->max_hz; in cadence_spi_set_speed()
147 if (priv->previous_hz != hz || in cadence_spi_set_speed()
148 priv->qspi_calibrated_hz != hz || in cadence_spi_set_speed()
150 err = spi_calibration(bus, hz); in cadence_spi_set_speed()
155 priv->previous_hz = hz; in cadence_spi_set_speed()
[all …]
/u-boot/arch/arm/mach-sunxi/
A Dclock_sun4i.c118 void clock_set_pll1(unsigned int hz) in clock_set_pll1() argument
126 while (pll1_para[i].freq > hz) in clock_set_pll1()
129 hz = pll1_para[i].freq; in clock_set_pll1()
130 if (! hz) in clock_set_pll1()
131 hz = 384000000; in clock_set_pll1()
134 axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ in clock_set_pll1()
135 ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */ in clock_set_pll1()
138 printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); in clock_set_pll1()
227 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) in clock_set_de_mod_clock() argument
232 while ((pll / div) > hz) in clock_set_de_mod_clock()
/u-boot/drivers/clk/rockchip/
A Dclk_rk3308.c88 if (old_rate > hz) { in rk3308_armclk_set_clk()
90 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
211 if (!hz) in rk3308_mac_set_clk()
212 hz = 50000000; in rk3308_mac_set_clk()
227 if (hz != 2500000 && hz != 25000000) { in rk3308_mac_set_speed_clk()
517 if (abs(hz - now) < abs(hz - best_rate)) { in rk3308_vop_set_clk()
526 if (best_rate != hz && hz == OSC_HZ) { in rk3308_vop_set_clk()
572 ulong hz) in rk3308_bus_set_clk() argument
635 ulong hz) in rk3308_peri_set_clk() argument
694 ulong hz) in rk3308_audio_set_clk() argument
[all …]
A Dclk_px30.c814 hz); in px30_vop_set_clk()
869 ulong hz) in px30_bus_set_clk() argument
935 ulong hz) in px30_peri_set_clk() argument
993 ulong hz) in px30_crypto_set_clk() argument
1040 ulong hz) in px30_i2s1_mclk_set_clk() argument
1044 if (hz != 12000000) { in px30_i2s1_mclk_set_clk()
1072 if (!hz) in px30_mac_set_clk()
1073 hz = 50000000; in px30_mac_set_clk()
1087 if (hz != 2500000 && hz != 25000000) { in px30_mac_set_speed_clk()
1136 if (old_rate > hz) { in px30_armclk_set_clk()
[all …]
A Dclk_rv1108.c42 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
43 #hz "Hz cannot be hit with PLL "\
210 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rv1108_saradc_set_clk()
235 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio1_set_clk()
261 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio0_set_clk()
296 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_dclk_vop_set_clk()
326 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_aclk_bus_set_clk()
378 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_aclk_peri_set_clk()
394 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_hclk_peri_set_clk()
409 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_pclk_peri_set_clk()
[all …]
A Dclk_rk3128.c33 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
35 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
371 static ulong rk3128_peri_set_pclk(struct rk3128_cru *cru, ulong clk_id, uint hz) in rk3128_peri_set_pclk() argument
375 src_clk_div = PERI_ACLK_HZ / hz; in rk3128_peri_set_pclk()
406 static ulong rk3128_saradc_set_clk(struct rk3128_cru *cru, uint hz) in rk3128_saradc_set_clk() argument
410 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3128_saradc_set_clk()
420 static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz) in rk3128_vop_set_clk() argument
425 src_clk_div = GPLL_HZ / hz; in rk3128_vop_set_clk()
442 if (pll_para_config(hz, &cpll_config)) in rk3128_vop_set_clk()
456 return hz; in rk3128_vop_set_clk()
A Dclk_rk3188.c78 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
79 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
80 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
81 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
125 unsigned int hz, bool has_bwadj) in rkclk_configure_ddr() argument
135 switch (hz) { in rkclk_configure_ddr()
171 unsigned int hz, bool has_bwadj) in rkclk_configure_cpu() argument
186 switch (hz) { in rkclk_configure_cpu()
226 return hz; in rkclk_configure_cpu()
A Dclk_rk3328.c37 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
39 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
365 static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz) in rk3328_i2c_set_clk() argument
369 src_clk_div = GPLL_HZ / hz; in rk3328_i2c_set_clk()
522 static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz) in rk3328_pwm_set_clk() argument
524 u32 div = GPLL_HZ / hz; in rk3328_pwm_set_clk()
545 static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz) in rk3328_saradc_set_clk() argument
549 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3328_saradc_set_clk()
569 static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz) in rk3328_spi_set_clk() argument
573 src_clk_div = GPLL_HZ / hz; in rk3328_spi_set_clk()
A Dclk_rk3368.c48 #define PLL_DIVISORS(hz, _nr, _no) { \ argument
49 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
50 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
51 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
405 static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz) in rk3368_spi_set_clk() argument
410 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); in rk3368_spi_set_clk()
443 static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz) in rk3368_saradc_set_clk() argument
447 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3368_saradc_set_clk()
/u-boot/drivers/clk/
A Dclk_pic32.c121 ulong hz; in pic32_get_sysclk() local
133 hz = SYS_FRC_CLK_HZ / div; in pic32_get_sysclk()
137 hz = pic32_get_pll_rate(priv); in pic32_get_sysclk()
141 hz = SYS_POSC_CLK_HZ; in pic32_get_sysclk()
145 hz = 0; in pic32_get_sysclk()
150 return hz; in pic32_get_sysclk()
/u-boot/drivers/mmc/
A Dsunxi_mmc.c102 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) in mmc_set_mod_clk() argument
120 if (hz <= 24000000) { in mmc_set_mod_clk()
136 div = pll_hz / hz; in mmc_set_mod_clk()
137 if (pll_hz % hz) in mmc_set_mod_clk()
148 hz); in mmc_set_mod_clk()
153 if (hz <= 400000) { in mmc_set_mod_clk()
156 } else if (hz <= 25000000) { in mmc_set_mod_clk()
160 } else if (hz <= 52000000) { in mmc_set_mod_clk()
168 } else if (hz <= 52000000) { in mmc_set_mod_clk()
198 priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div); in mmc_set_mod_clk()

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