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Searched refs:mc (Results 1 – 25 of 64) sorted by relevance

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/u-boot/arch/x86/lib/
A Dmpspec.c29 ulong mc; in mp_write_floating_table() local
53 mc->mpc_spec = MPSPEC_V14; in mp_config_table_init()
54 mc->mpc_checksum = 0; in mp_config_table_init()
55 mc->mpc_oemptr = 0; in mp_config_table_init()
56 mc->mpc_oemsize = 0; in mp_config_table_init()
57 mc->mpc_entry_count = 0; in mp_config_table_init()
59 mc->mpe_length = 0; in mp_config_table_init()
60 mc->mpe_checksum = 0; in mp_config_table_init()
61 mc->reserved = 0; in mp_config_table_init()
225 mc->mpe_checksum = table_compute_checksum((void *)mp_next_mpc_entry(mc), in mptable_finalize()
[all …]
/u-boot/arch/x86/include/asm/
A Dmpspec.h228 return (ulong)mc + mc->mpc_length; in mp_next_mpc_entry()
242 mc->mpc_length += length; in mp_add_mpc_entry()
243 mc->mpc_entry_count++; in mp_add_mpc_entry()
258 return (ulong)mc + mc->mpc_length + mc->mpe_length; in mp_next_mpe_entry()
270 static inline void mp_add_mpe_entry(struct mp_config_table *mc, in mp_add_mpe_entry() argument
273 mc->mpe_length += mpe->mpe_length; in mp_add_mpe_entry()
295 void mp_config_table_init(struct mp_config_table *mc);
304 void mp_write_processor(struct mp_config_table *mc);
391 void mp_write_address_space(struct mp_config_table *mc,
406 void mp_write_bus_hierarchy(struct mp_config_table *mc,
[all …]
/u-boot/arch/arm/include/asm/arch-mx6/
A Dmx6-pins.h10 #define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \ argument
11 prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc)
15 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ argument
16 MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc),
19 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ argument
20 MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc),
25 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ argument
26 MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
31 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ argument
32 MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
/u-boot/arch/arm/mach-tegra/
A Dap.c175 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; in protect_secure_section() local
187 static void smmu_flush(struct mc_ctlr *mc) in smmu_flush() argument
189 (void)readl(&mc->mc_smmu_config); in smmu_flush()
194 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; in smmu_enable() local
202 writel(0xffffffff, &mc->mc_smmu_translation_enable_0); in smmu_enable()
203 writel(0xffffffff, &mc->mc_smmu_translation_enable_1); in smmu_enable()
204 writel(0xffffffff, &mc->mc_smmu_translation_enable_2); in smmu_enable()
205 writel(0xffffffff, &mc->mc_smmu_translation_enable_3); in smmu_enable()
211 value = readl(&mc->mc_smmu_config); in smmu_enable()
213 writel(value, &mc->mc_smmu_config); in smmu_enable()
[all …]
A Dgpu.c21 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; in tegra_gpu_config() local
28 writel(0, &mc->mc_video_protect_size_mb); in tegra_gpu_config()
30 &mc->mc_video_protect_reg_ctrl); in tegra_gpu_config()
32 readl(&mc->mc_video_protect_reg_ctrl); in tegra_gpu_config()
A Dboard.c91 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE; in tegra_cpu_is_non_secure() local
92 uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0); in tegra_cpu_is_non_secure()
101 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE; in query_sdram_size() local
105 emem_cfg = readl(&mc->mc_emem_cfg); in query_sdram_size()
/u-boot/board/gdsys/mpc8308/
A Dgazerbeam.c49 int mc = 0; in board_early_init_r() local
61 sysinfo_get_int(sysinfo, BOARD_MULTICHANNEL, &mc); in board_early_init_r()
64 if (mc == 2 || mc == 1) in board_early_init_r()
67 if (mc == 4) { in board_early_init_r()
73 if (mc == 2 || con == VAR_CON) { in board_early_init_r()
92 int mc = 0; in checksysinfo() local
98 sysinfo_get_int(sysinfo, BOARD_MULTICHANNEL, &mc); in checksysinfo()
102 printf("%s ", mc == 4 ? "MC4" : mc == 2 ? "MC2" : "SC"); in checksysinfo()
/u-boot/board/nvidia/nyan-big/
A Dnyan-big.c75 struct mc_ctlr *mc = (void *)NV_PA_MC_BASE; in setup_kernel_info() local
78 writel(0, &mc->mc_video_protect_bom); in setup_kernel_info()
79 writel(0, &mc->mc_video_protect_size_mb); in setup_kernel_info()
80 writel(1, &mc->mc_video_protect_reg_ctrl); in setup_kernel_info()
/u-boot/drivers/nvme/
A Dnvme_show.c96 static void print_metadata_cap(u8 mc, int devnum) in print_metadata_cap() argument
100 mc & 0x02 ? "yes" : "No"); in print_metadata_cap()
102 mc & 0x01 ? "yes" : "No"); in print_metadata_cap()
126 print_metadata_cap(id->mc, ns->devnum); in nvme_print_info()
/u-boot/arch/arm/dts/
A Dfsl-lx2160a.dtsi419 fsl_mc: fsl-mc@80c000000 {
439 compatible = "fsl,qoriq-mc-dpmac";
445 compatible = "fsl,qoriq-mc-dpmac";
451 compatible = "fsl,qoriq-mc-dpmac";
457 compatible = "fsl,qoriq-mc-dpmac";
463 compatible = "fsl,qoriq-mc-dpmac";
469 compatible = "fsl,qoriq-mc-dpmac";
475 compatible = "fsl,qoriq-mc-dpmac";
481 compatible = "fsl,qoriq-mc-dpmac";
487 compatible = "fsl,qoriq-mc-dpmac";
[all …]
A Dfsl-ls1088a.dtsi245 fsl_mc: fsl-mc@80c000000 {
265 compatible = "fsl,qoriq-mc-dpmac";
271 compatible = "fsl,qoriq-mc-dpmac";
277 compatible = "fsl,qoriq-mc-dpmac";
283 compatible = "fsl,qoriq-mc-dpmac";
289 compatible = "fsl,qoriq-mc-dpmac";
295 compatible = "fsl,qoriq-mc-dpmac";
301 compatible = "fsl,qoriq-mc-dpmac";
307 compatible = "fsl,qoriq-mc-dpmac";
313 compatible = "fsl,qoriq-mc-dpmac";
[all …]
A Dfsl-ls2080a.dtsi248 fsl_mc: fsl-mc@80c000000 {
249 compatible = "fsl,qoriq-mc", "simple-mfd";
268 compatible = "fsl,qoriq-mc-dpmac";
274 compatible = "fsl,qoriq-mc-dpmac";
280 compatible = "fsl,qoriq-mc-dpmac";
286 compatible = "fsl,qoriq-mc-dpmac";
292 compatible = "fsl,qoriq-mc-dpmac";
298 compatible = "fsl,qoriq-mc-dpmac";
304 compatible = "fsl,qoriq-mc-dpmac";
310 compatible = "fsl,qoriq-mc-dpmac";
A Dns3-board.dts8 #include <dt-bindings/memory/bcm-ns3-mc.h>
A Ddm816x.dtsi414 reg-names = "mc", "control";
416 interrupt-names = "mc";
454 reg-names = "mc", "control";
456 interrupt-names = "mc";
A Dtegra114.dtsi3 #include <dt-bindings/memory/tegra114-mc.h>
54 iommus = <&mc TEGRA_SWGROUP_DC>;
73 iommus = <&mc TEGRA_SWGROUP_DCB>;
522 mc: memory-controller@70019000 { label
523 compatible = "nvidia,tegra114-mc";
526 clock-names = "mc";
A Dtegra124.dtsi3 #include <dt-bindings/memory/tegra124-mc.h>
107 iommus = <&mc TEGRA_SWGROUP_DC>;
122 iommus = <&mc TEGRA_SWGROUP_DCB>;
192 iommus = <&mc TEGRA_SWGROUP_GPU>;
592 mc: memory-controller@70019000 { label
593 compatible = "nvidia,tegra124-mc";
596 clock-names = "mc";
607 nvidia,memory-controller = <&mc>;
A Dtegra210.dtsi3 #include <dt-bindings/memory/tegra210-mc.h>
129 iommus = <&mc TEGRA_SWGROUP_DC>;
144 iommus = <&mc TEGRA_SWGROUP_DCB>;
302 iommus = <&mc TEGRA_SWGROUP_GPU>;
665 mc: memory-controller@70019000 { label
666 compatible = "nvidia,tegra210-mc";
669 clock-names = "mc";
A Dmt8518.dtsi86 interrupt-names = "mc";
/u-boot/drivers/net/fsl-mc/dpio/
A Dqbman_portal.c77 p->mc.check = swp_mc_can_start; in qbman_swp_init()
79 p->mc.valid_bit = QB_VALID_BIT; in qbman_swp_init()
123 BUG_ON(p->mc.check != swp_mc_can_start); in qbman_swp_mc_start()
129 p->mc.check = swp_mc_can_submit; in qbman_swp_mc_start()
138 BUG_ON(p->mc.check != swp_mc_can_submit); in qbman_swp_mc_submit()
146 *v = cmd_verb | p->mc.valid_bit; in qbman_swp_mc_submit()
150 p->mc.check = swp_mc_can_poll; in qbman_swp_mc_submit()
158 BUG_ON(p->mc.check != swp_mc_can_poll); in qbman_swp_mc_result()
160 ret = qbman_cena_read(&p->sys, QBMAN_CENA_SWP_RR(p->mc.valid_bit)); in qbman_swp_mc_result()
166 p->mc.check = swp_mc_can_start; in qbman_swp_mc_result()
[all …]
A Dqbman_portal.h39 } mc; member
/u-boot/drivers/net/fsl-mc/
A DMakefile7 obj-y += mc.o \
/u-boot/drivers/usb/musb-new/
A Dpic32.c224 struct fdt_resource mc, glue; in musb_usb_probe() local
233 "mc", &mc); in musb_usb_probe()
246 mregs = ioremap(mc.start, fdt_resource_size(&mc)); in musb_usb_probe()
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
A DREADME.lsch3132 executed. The commmand is demostrated taking an example of mc boot
139 setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000'
143 setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000'
325 (MC). These commands are used to start mc, aiop and apply DPL
332 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
338 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
345 => fsl_mc start mc 580300000 580800000
350 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
359 => fsl_mc start mc 580300000 580800000
366 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
[all …]
/u-boot/arch/riscv/dts/
A Dfu540-c000.dtsi41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
65 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
89 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
113 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
A Dmicrochip-mpfs-icicle-kit.dts53 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
84 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
115 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
146 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";

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