Home
last modified time | relevance | path

Searched refs:msr (Results 1 – 25 of 63) sorted by relevance

123

/u-boot/arch/x86/cpu/ivybridge/
A Dmodel_206ax.c37 msr_t msr; in enable_vmx() local
57 msr.hi = 0; in enable_vmx()
58 msr.lo = 0; in enable_vmx()
226 msr_t msr; in configure_c_states() local
254 msr.hi = 0; in configure_c_states()
287 msr_t msr; in configure_misc() local
308 msr_t msr; in enable_lapic_tpr() local
318 msr_t msr; in configure_dca_cap() local
331 msr_t msr; in set_max_ratio() local
349 msr_t msr; in set_energy_perf_bias() local
[all …]
/u-boot/arch/x86/cpu/broadwell/
A Dcpu_full.c168 msr_t msr; in initialize_vr_config() local
366 msr_t msr; in broadwell_init() local
388 msr_t msr; in configure_mca() local
395 msr.lo = 0; in configure_mca()
396 msr.hi = 0; in configure_mca()
408 msr_t msr; in enable_lapic_tpr() local
417 msr_t msr; in configure_c_states() local
474 msr_t msr; in configure_misc() local
496 msr_t msr; in configure_dca_cap() local
509 msr_t msr; in set_energy_perf_bias() local
[all …]
A Dcpu.c47 msr_t msr, perf_ctl; in set_max_freq() local
51 msr = msr_read(MSR_CONFIG_TDP_NOMINAL); in set_max_freq()
52 perf_ctl.lo = (msr.lo & 0xff) << 8; in set_max_freq()
55 msr = msr_read(MSR_PLATFORM_INFO); in set_max_freq()
56 perf_ctl.lo = msr.lo & 0xff00; in set_max_freq()
/u-boot/arch/x86/cpu/intel_common/
A Dcpu.c125 msr_t msr; in cpu_intel_get_info() local
139 msr_t msr; in cpu_configure_thermal_target() local
180 msr_t msr; in cpu_set_p_state_to_turbo_ratio() local
190 msr_t msr; in cpu_get_burst_mode_state() local
212 msr_t msr; in cpu_set_burst_mode() local
224 msr_t msr; in cpu_set_eist() local
241 msr_t msr; in cpu_get_min_ratio() local
252 msr_t msr; in cpu_get_max_ratio() local
279 msr_t msr; in cpu_get_power_max() local
290 msr_t msr; in cpu_get_max_turbo_ratio() local
[all …]
/u-boot/arch/x86/include/asm/
A Dmsr.h26 struct msr { struct
38 struct msr reg; argument
39 struct msr *msrs;
137 wrmsrl(msr, val); in msr_clrsetbits_64()
146 wrmsrl(msr, val); in msr_setbits_64()
155 wrmsrl(msr, val); in msr_clrbits_64()
173 gprs[1] = msr; in rdmsrl_amd_safe()
188 gprs[1] = msr; in wrmsrl_amd_safe()
214 rdmsr(msr_num, msr.lo, msr.hi); in msr_read()
216 return msr; in msr_read()
[all …]
/u-boot/arch/x86/cpu/apollolake/
A Dcpu_common.c17 struct msr_t msr; in cpu_flush_l1d_to_l2() local
19 msr = msr_read(MSR_POWER_MISC); in cpu_flush_l1d_to_l2()
20 msr.lo |= FLUSH_DL1_L2; in cpu_flush_l1d_to_l2()
21 msr_write(MSR_POWER_MISC, msr); in cpu_flush_l1d_to_l2()
27 msr_t msr; in enable_pm_timer_emulation() local
36 msr.hi = (3579545ULL << 32) / CTC_FREQ; in enable_pm_timer_emulation()
39 msr.lo = EMULATE_PM_TMR_EN | (upriv->acpi_base + R_ACPI_PM1_TMR); in enable_pm_timer_emulation()
40 debug("PM timer %x %x\n", msr.hi, msr.lo); in enable_pm_timer_emulation()
41 msr_write(MSR_EMULATE_PM_TIMER, msr); in enable_pm_timer_emulation()
/u-boot/arch/arm/include/asm/
A Dmacro.h160 msr cntvoff_el2, xzr
172 msr sctlr_el2, \tmp
200 msr scr_el3, \tmp
206 msr spsr_el3, \tmp
207 msr elr_el3, \ep
218 msr scr_el3, \tmp
225 msr spsr_el3, \tmp
252 msr vpidr_el2, \tmp
292 msr hcr_el2, \tmp
298 msr spsr_el2, \tmp
[all …]
/u-boot/arch/x86/cpu/
A Dlapic.c69 msr_t msr; in enable_lapic() local
71 msr = msr_read(MSR_IA32_APICBASE); in enable_lapic()
72 msr.hi &= 0xffffff00; in enable_lapic()
73 msr.lo |= MSR_IA32_APICBASE_ENABLE; in enable_lapic()
74 msr.lo &= ~MSR_IA32_APICBASE_BASE; in enable_lapic()
75 msr.lo |= LAPIC_DEFAULT_BASE; in enable_lapic()
76 msr_write(MSR_IA32_APICBASE, msr); in enable_lapic()
83 msr_t msr; in disable_lapic() local
85 msr = msr_read(MSR_IA32_APICBASE); in disable_lapic()
86 msr.lo &= ~MSR_IA32_APICBASE_ENABLE; in disable_lapic()
[all …]
A Dturbo.c58 msr_t msr; in turbo_get_state() local
68 msr = msr_read(MSR_IA32_MISC_ENABLE); in turbo_get_state()
69 turbo_en = !(msr.hi & MISC_DISABLE_TURBO); in turbo_get_state()
91 msr_t msr; in turbo_enable() local
96 msr = msr_read(MSR_IA32_MISC_ENABLE); in turbo_enable()
97 msr.hi &= ~MISC_DISABLE_TURBO; in turbo_enable()
98 msr_write(MSR_IA32_MISC_ENABLE, msr); in turbo_enable()
/u-boot/arch/powerpc/cpu/mpc8xx/
A Dtraps.c62 regs->msr, regs->msr & MSR_EE ? 1 : 0, in show_regs()
63 regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0, in show_regs()
64 regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0, in show_regs()
65 regs->msr & MSR_DR ? 1 : 0); in show_regs()
102 switch (regs->msr & 0x000F0000) { in MachineCheckException()
149 regs->nip, regs->msr, regs->trap); in UnknownException()
/u-boot/arch/arm/cpu/armv8/
A Dstart.S113 msr \regname, \reg
128 msr scr_el3, x0
129 msr cptr_el3, xzr /* Enable FP/SIMD */
137 msr cptr_el2, x0 /* Enable FP/SIMD */
155 msr S3_1_c15_c2_1, x0
211 msr sctlr_el3, x0
214 msr sctlr_el2, x0
217 msr sctlr_el1, x0
389 3: msr vbar_el3, x0
391 2: msr vbar_el2, x0
[all …]
A Dcache.S27 msr csselr_el1, x12 /* select cache level */
99 msr csselr_el1, x0 /* restore csselr_el1 */
234 3: msr sctlr_el3, x1
236 2: msr sctlr_el2, x1
238 1: msr sctlr_el1, x1
249 3: msr ttbr0_el3, x0
251 2: msr ttbr0_el2, x0
253 1: msr ttbr0_el1, x0
258 3: msr sctlr_el3, x2
260 2: msr sctlr_el2, x2
[all …]
/u-boot/arch/powerpc/lib/
A Dkgdb.c83 unsigned long msr; in kgdb_enter() local
85 kdp->private[0] = msr = get_msr(); in kgdb_enter()
86 set_msr(msr & ~MSR_EE); /* disable interrupts */ in kgdb_enter()
92 regs->msr &= ~MSR_SE; in kgdb_enter()
109 unsigned long msr = kdp->private[0]; in kgdb_exit() local
118 set_msr(msr); in kgdb_exit()
122 regs->msr |= MSR_SE; in kgdb_exit()
124 set_msr(msr | MSR_SE); in kgdb_exit()
173 *ptr++ = regs->msr; in kgdb_getregs()
206 case 65: regs->msr = *ptr; break; in kgdb_putreg()
[all …]
A Dinterrupts.c51 ulong msr = get_msr (); in disable_interrupts() local
53 set_msr (msr & ~MSR_EE); in disable_interrupts()
54 return ((msr & MSR_EE) != 0); in disable_interrupts()
/u-boot/arch/powerpc/cpu/mpc83xx/
A Dtraps.c60 regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, in show_regs()
61 regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, in show_regs()
62 regs->msr&MSR_IR ? 1 : 0, in show_regs()
63 regs->msr&MSR_DR ? 1 : 0); in show_regs()
137 switch( regs->msr & 0x000F0000) { in MachineCheckException()
203 regs->nip, regs->msr, regs->trap); in UnknownException()
A Dcpu.c130 ulong msr; in do_reset() local
136 msr = mfmsr(); in do_reset()
137 msr &= ~(MSR_EE | MSR_IR | MSR_DR); in do_reset()
138 mtmsr(msr); in do_reset()
/u-boot/arch/powerpc/cpu/mpc86xx/
A Dtraps.c70 regs->msr, regs->msr & MSR_EE ? 1 : 0, in show_regs()
71 regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0, in show_regs()
72 regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0, in show_regs()
73 regs->msr & MSR_DR ? 1 : 0); in show_regs()
117 switch ( regs->msr & 0x001F0000) { in MachineCheckException()
197 regs->nip, regs->msr, regs->trap); in UnknownException()
/u-boot/arch/x86/cpu/baytrail/
A Dcpu.c70 msr_t msr; in set_max_freq() local
73 msr = msr_read(MSR_IA32_MISC_ENABLE); in set_max_freq()
74 msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP; in set_max_freq()
75 msr_write(MSR_IA32_MISC_ENABLE, msr); in set_max_freq()
81 msr = msr_read(MSR_IACORE_RATIOS); in set_max_freq()
82 perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; in set_max_freq()
88 msr = msr_read(MSR_IACORE_VIDS); in set_max_freq()
89 perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; in set_max_freq()
/u-boot/arch/powerpc/include/asm/
A Dppc.h105 unsigned long msr; in get_msr() local
107 asm volatile ("mfmsr %0" : "=r" (msr) : ); in get_msr()
109 return msr; in get_msr()
112 static inline void set_msr(unsigned long msr) in set_msr() argument
114 asm volatile ("mtmsr %0" : : "r" (msr)); in set_msr()
A Dptrace.h29 PPC_REG msr; member
50 #define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
/u-boot/arch/powerpc/cpu/mpc85xx/
A Dtraps.c98 regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, in show_regs()
99 regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, in show_regs()
100 regs->msr&MSR_IR ? 1 : 0, in show_regs()
101 regs->msr&MSR_DR ? 1 : 0); in show_regs()
261 regs->nip, regs->msr, regs->trap); in UnknownException()
277 regs->nip, regs->msr, regs->trap); in ExtIntException()
/u-boot/arch/arm/lib/
A Dgic_64.S116 msr ICC_SRE_EL3, x10
120 msr ICC_IGRPEN1_EL3, x10
123 msr ICC_CTLR_EL3, xzr
129 msr ICC_SRE_EL2, x10
132 msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */
136 msr ICC_PMR_EL1, x10
172 msr ICC_ASGI1R_EL1, x9
/u-boot/arch/arm/mach-imx/
A Dlowlevel.S14 msr daifclr, #4
19 msr hcr_el2, x0
/u-boot/arch/arm/cpu/arm926ejs/mxs/
A Dstart.S71 msr cpsr, r2
77 msr cpsr,r2
/u-boot/drivers/sysreset/
A Dsysreset_mpc83xx.c30 ulong msr; in __do_reset() local
38 msr = mfmsr(); in __do_reset()
39 msr &= ~(MSR_EE | MSR_IR | MSR_DR); in __do_reset()
40 mtmsr(msr); in __do_reset()

Completed in 49 milliseconds

123