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Searched refs:phy_base (Results 1 – 17 of 17) sorted by relevance

/u-boot/drivers/ram/rockchip/
A Dsdram_phy_px30.c24 setbits_le32(PHY_REG(phy_base, j), 1 << 4); in sdram_phy_dll_bypass_set()
47 writel(tmp, PHY_REG(phy_base, j)); in sdram_phy_dll_bypass_set()
72 writel(cmd_drv, PHY_REG(phy_base, 0x11)); in sdram_phy_set_ds_odt()
74 writel(clk_drv, PHY_REG(phy_base, 0x16)); in sdram_phy_set_ds_odt()
75 writel(clk_drv, PHY_REG(phy_base, 0x18)); in sdram_phy_set_ds_odt()
79 writel(dqs_drv, PHY_REG(phy_base, j)); in sdram_phy_set_ds_odt()
114 phy_soft_reset(phy_base); in phy_dram_set_bw()
128 writel(0, PHY_REG(phy_base, j + 0xe)); in phy_data_training()
142 ret = readl(PHY_REG(phy_base, 0xff)); in phy_data_training()
171 void phy_cfg(void __iomem *phy_base, in phy_cfg() argument
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A Dsdram_rk3328.c122 void __iomem *phy_base = dram->phy; in rkclk_configure_ddr() local
125 clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7); in rkclk_configure_ddr()
261 void __iomem *phy_base = dram->phy; in rx_deskew_switch_adjust() local
264 gate_val = MAX(readl(PHY_REG(phy_base, 0xfb + i)), gate_val); in rx_deskew_switch_adjust()
268 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2); in rx_deskew_switch_adjust()
269 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4, in rx_deskew_switch_adjust()
275 void __iomem *phy_base = dram->phy; in tx_deskew_switch_adjust() local
277 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1); in tx_deskew_switch_adjust()
A Dsdram_px30.c319 void __iomem *phy_base = dram->phy; in check_rd_gate() local
326 bw = (readl(PHY_REG(phy_base, 0x0)) >> 4) & 0xf; in check_rd_gate()
341 gate[i] = readl(PHY_REG(phy_base, 0xfb + i)); in check_rd_gate()
437 void __iomem *phy_base = dram->phy; in enable_low_power() local
464 setbits_le32(PHY_REG(phy_base, 7), 1 << 7); in enable_low_power()
/u-boot/arch/arm/mach-uniphier/dram/
A Dddrphy-ld4.c48 writel(0x0300c473, phy_base + PHY_PGCR1); in uniphier_ld4_ddrphy_init()
49 writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0); in uniphier_ld4_ddrphy_init()
51 writel(0x00083DEF, phy_base + PHY_PTR2); in uniphier_ld4_ddrphy_init()
54 writel(0xF004001A, phy_base + PHY_DSGCR); in uniphier_ld4_ddrphy_init()
57 tmp = readl(phy_base + PHY_DXCCR); in uniphier_ld4_ddrphy_init()
60 writel(tmp, phy_base + PHY_DXCCR); in uniphier_ld4_ddrphy_init()
62 writel(0x0000040B, phy_base + PHY_DCR); in uniphier_ld4_ddrphy_init()
66 writel(ddrphy_mr0[freq_e], phy_base + PHY_MR0); in uniphier_ld4_ddrphy_init()
67 writel(0x00000006, phy_base + PHY_MR1); in uniphier_ld4_ddrphy_init()
68 writel(ddrphy_mr2[freq_e], phy_base + PHY_MR2); in uniphier_ld4_ddrphy_init()
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A Dumc-pxs2.c64 tmp = readl(phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
66 writel(tmp, phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
71 writel(tmp, phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
80 tmp = readl(phy_base + MPHY_PGCR1); in ddrphy_vt_ctrl()
87 writel(tmp, phy_base + MPHY_PGCR1); in ddrphy_vt_ctrl()
101 ddrphy_vt_ctrl(phy_base, 0); in ddrphy_dqs_delay_fixup()
113 ddrphy_vt_ctrl(phy_base, 1); in ddrphy_dqs_delay_fixup()
208 zq_base = phy_base + MPHY_ZQ_BASE; in ddrphy_init()
565 ddrphy_dram_init(phy_base); in umc_ch_init()
575 ret = ddrphy_training(phy_base); in umc_ch_init()
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A Dddrphy-training.c21 void ddrphy_prepare_training(void __iomem *phy_base, int rank) in ddrphy_prepare_training() argument
23 void __iomem *dx_base = phy_base + PHY_DX_BASE; in ddrphy_prepare_training()
37 tmp = readl(phy_base + PHY_DTCR); in ddrphy_prepare_training()
46 writel(tmp, phy_base + PHY_DTCR); in ddrphy_prepare_training()
107 int ddrphy_training(void __iomem *phy_base) in ddrphy_training() argument
123 writel(init_flag, phy_base + PHY_PIR); in ddrphy_training()
131 pgsr0 = readl(phy_base + PHY_PGSR0); in ddrphy_training()
A Dddrphy-init.h12 int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus);
13 void ddrphy_prepare_training(void __iomem *phy_base, int rank);
14 int ddrphy_training(void __iomem *phy_base);
A Dcmd_ddrmphy.c73 void __iomem *phy_base, *dx_base; in dump_loop() local
77 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
78 dx_base = phy_base + MPHY_DX_BASE; in dump_loop()
87 iounmap(phy_base); in dump_loop()
93 void __iomem *phy_base, *zq_base; in zq_dump() local
102 zq_base = phy_base + MPHY_ZQ_BASE; in zq_dump()
123 iounmap(phy_base); in zq_dump()
236 void __iomem *reg = phy_base + ofst; \
242 void __iomem *phy_base; in reg_dump() local
251 ptr_to_uint(phy_base)); in reg_dump()
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A Dcmd_ddrphy.c88 void __iomem *phy_base, *dx_base; in dump_loop() local
92 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
93 dx_base = phy_base + PHY_DX_BASE; in dump_loop()
102 iounmap(phy_base); in dump_loop()
203 { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
211 void __iomem *reg = phy_base + ofst; \
218 void __iomem *phy_base; in reg_dump() local
224 phy_base = ioremap(param->phy[phy].base, SZ_4K); in reg_dump()
227 phy, ptr_to_uint(phy_base)); in reg_dump()
260 iounmap(phy_base); in reg_dump()
A Dumc-pro4.c133 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
145 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
149 ddrphy_prepare_training(phy_base, phy); in umc_ch_init()
150 ret = ddrphy_training(phy_base); in umc_ch_init()
154 phy_base += 0x00001000; in umc_ch_init()
A Dumc-ld4.c146 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
155 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
159 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
160 ret = ddrphy_training(phy_base); in umc_ch_init()
A Dumc-sld8.c149 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
158 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
162 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
163 ret = ddrphy_training(phy_base); in umc_ch_init()
/u-boot/arch/arm/include/asm/arch-rockchip/
A Dsdram_phy_px30.h59 void phy_soft_reset(void __iomem *phy_base);
60 void phy_dram_set_bw(void __iomem *phy_base, u32 bw);
61 void phy_cfg(void __iomem *phy_base,
64 int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype);
/u-boot/drivers/phy/
A Domap-usb2-phy.c48 void *phy_base; member
165 val = readl(priv->phy_base + USB2PHY_ANA_CONFIG1); in omap_usb2_phy_init()
167 writel(val, priv->phy_base + USB2PHY_ANA_CONFIG1); in omap_usb2_phy_init()
171 val = readl(priv->phy_base + USB2PHY_CHRG_DET); in omap_usb2_phy_init()
173 writel(val, priv->phy_base + USB2PHY_CHRG_DET); in omap_usb2_phy_init()
218 priv->phy_base = dev_read_addr_ptr(dev); in omap_usb2_phy_probe()
220 if (!priv->phy_base) in omap_usb2_phy_probe()
/u-boot/drivers/usb/host/
A Dxhci-exynos5.c40 fdt_addr_t phy_base; member
83 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); in xhci_usb_of_to_plat()
84 if (plat->phy_base == FDT_ADDR_T_NONE) { in xhci_usb_of_to_plat()
215 ctx->usb3_phy = (struct exynos_usb3_phy *)plat->phy_base; in xhci_usb_probe()
A Dehci-exynos.c33 fdt_addr_t phy_base; member
74 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); in ehci_usb_of_to_plat()
75 if (plat->phy_base == FDT_ADDR_T_NONE) { in ehci_usb_of_to_plat()
223 ctx->usb = (struct exynos_usb_phy *)plat->phy_base; in ehci_usb_probe()
/u-boot/arch/arm/dts/
A Dqcom-ipq4019.dtsi145 reg-names = "phy_base";
155 reg-names = "phy_base";
188 reg-names = "phy_base";

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