Searched refs:pll_enet (Results 1 – 6 of 6) sorted by relevance
138 reg = readl(&anatop->pll_enet); in setup_fec()140 writel(reg, &anatop->pll_enet); in setup_fec()
148 reg = readl(&ccm_anatop->pll_enet); in decode_pll()304 reg = readl(&ccm_anatop->pll_enet); in mxc_get_pll_enet_derive()747 reg = readl(&ccm_anatop->pll_enet); in enable_pll_enet()751 writel(reg, &ccm_anatop->pll_enet); in enable_pll_enet()754 if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK) in enable_pll_enet()
289 reg = readl(&anatop->pll_enet); in setup_fec()291 writel(reg, &anatop->pll_enet); in setup_fec()
918 reg = readl(&anatop->pll_enet); in enable_fec_anatop_clock()936 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()938 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) in enable_fec_anatop_clock()951 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()
832 u32 pll_enet; /* 0x0e0 */ member
112 uint32_t pll_enet; /* offset 0x00e0 */ member
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