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Searched refs:reg (Results 1 – 25 of 2020) sorted by relevance

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/u-boot/drivers/ddr/marvell/axp/
A Dddr3_dfs.c71 u32 reg; in wait_refresh_op_complete() local
185 } while (reg); in ddr3_dfs_high_2_low()
272 reg = 0x0000FDFF; in ddr3_dfs_high_2_low()
280 reg = 0x0000FF00; in ddr3_dfs_high_2_low()
299 reg = 0x000FFF02; in ddr3_dfs_high_2_low()
314 reg = 0x0102FDFF; in ddr3_dfs_high_2_low()
333 reg = 0x000000FF; in ddr3_dfs_high_2_low()
423 } while (reg); in ddr3_dfs_high_2_low()
507 reg = 0x0000FF00; in ddr3_dfs_high_2_low()
1118 } while (reg); in ddr3_dfs_low_2_high()
[all …]
A Dddr3_write_leveling.c116 reg = in ddr3_write_leveling_hw()
127 reg = in ddr3_write_leveling_hw()
252 reg = in ddr3_wl_supplement()
256 reg |= in ddr3_wl_supplement()
401 reg = in ddr3_wl_supplement()
539 reg = in ddr3_write_leveling_hw_reg_dimm()
563 reg = in ddr3_write_leveling_hw_reg_dimm()
730 reg = in ddr3_write_leveling_sw()
738 reg = in ddr3_write_leveling_sw()
964 reg = in ddr3_write_leveling_sw_reg_dimm()
[all …]
A Dddr3_hw_training.c85 u32 freq, reg; in ddr3_hw_training() local
136 reg = (((reg >> 1) & 0xE) | (reg & 0x1)) & 0xF; in ddr3_hw_training()
551 u32 reg = 0; in ddr3_write_pup_reg() local
575 reg = 0; in ddr3_write_pup_reg()
592 } while (reg); in ddr3_write_pup_reg()
601 u32 reg; in ddr3_read_pup_reg() local
623 u32 reg; in ddr3_load_patterns() local
917 u32 freq, reg; in ddr3_training_suspend_resume() local
1071 u32 reg, mask; in ddr3_odt_activate() local
1078 reg |= mask; in ddr3_odt_activate()
[all …]
/u-boot/drivers/video/exynos/
A Dexynos_dp_lowlevel.c24 unsigned int reg; in exynos_dp_enable_video_input() local
41 unsigned int reg; in exynos_dp_enable_video_bist() local
57 unsigned int reg; in exynos_dp_enable_video_mute() local
72 unsigned int reg; in exynos_dp_init_analog_param() local
198 reg |= AUX_PD; in exynos_dp_set_analog_power_down()
327 reg = INT_HPD; in exynos_dp_init_hpd()
434 reg |= AUX_EN; in exynos_dp_start_aux_transaction()
482 reg = BUF_CLR; in exynos_dp_write_byte_to_dpcd()
523 reg = BUF_CLR; in exynos_dp_read_byte_from_dpcd()
567 reg = BUF_CLR; in exynos_dp_write_bytes_to_dpcd()
[all …]
A Dexynos_mipi_dsi_lowlevel.c21 unsigned int reg; in exynos_mipi_dsi_func_reset() local
28 reg |= DSIM_FUNCRST; in exynos_mipi_dsi_func_reset()
42 reg |= DSIM_SWRST; in exynos_mipi_dsi_sw_reset()
67 reg |= mode; in exynos_mipi_dsi_set_interrupt_mask()
69 reg &= ~mode; in exynos_mipi_dsi_set_interrupt_mask()
77 unsigned int reg; in exynos_mipi_dsi_init_fifo_pointer() local
85 reg |= cfg; in exynos_mipi_dsi_init_fifo_pointer()
105 unsigned int reg; in exynos_mipi_dsi_set_main_disp_resol() local
124 unsigned int reg; in exynos_mipi_dsi_set_main_disp_vporch() local
142 unsigned int reg; in exynos_mipi_dsi_set_main_disp_hporch() local
[all …]
/u-boot/arch/arm/mach-tegra/tegra20/
A Dwarmboot_avp.c34 u32 reg; in wb_start() local
76 reg |= CPU_CLMP; in wb_start()
84 reg |= CPU_RST; in wb_start()
158 if (reg > 26) in wb_start()
159 reg = 19; in wb_start()
163 reg = 0; in wb_start()
165 reg = 1; in wb_start()
169 reg = scratch3.pllx_base_divn << reg; in wb_start()
173 reg = reg >> scratch3.pllx_base_divp; in wb_start()
178 if (reg > 600) in wb_start()
[all …]
/u-boot/arch/arm/dts/
A Darmada-38x-controlcenterdc.dts132 reg = <0>;
135 reg = <1>;
138 reg = <2>;
141 reg = <3>;
144 reg = <4>;
169 reg = <0>;
172 reg = <1>;
175 reg = <2>;
221 reg = <1>;
225 reg = <0>;
[all …]
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dfsl_lsch2_serdes.c183 reg &= 0xFF9FFFFF; in setup_serdes_volt()
193 reg &= 0xFF9FFFFF; in setup_serdes_volt()
203 reg &= 0xFFFFFFBF; in setup_serdes_volt()
204 reg |= 0x10000000; in setup_serdes_volt()
209 reg &= 0xFFFFFF1F; in setup_serdes_volt()
219 reg &= 0xFFFFFFBF; in setup_serdes_volt()
220 reg |= 0x10000000; in setup_serdes_volt()
234 reg &= 0xF7FFFFFF; in setup_serdes_volt()
237 reg &= 0xF7FFFFFF; in setup_serdes_volt()
243 reg &= 0xF7FFFFFF; in setup_serdes_volt()
[all …]
/u-boot/arch/x86/include/asm/arch-quark/
A Dmsg_port.h44 void msg_port_setup(int op, int port, int reg);
54 u32 msg_port_read(u8 port, u32 reg);
73 u32 msg_port_alt_read(u8 port, u32 reg);
92 u32 msg_port_io_read(u8 port, u32 reg);
109 msg_port_##type##_write(port, reg, \
110 (msg_port_##type##_read(port, reg) \
113 #define msg_port_clrbits(port, reg, clr) \ argument
115 #define msg_port_setbits(port, reg, set) \ argument
120 #define msg_port_alt_clrbits(port, reg, clr) \ argument
127 #define msg_port_io_clrbits(port, reg, clr) \ argument
[all …]
/u-boot/drivers/watchdog/
A Dorion_wdt.c30 void __iomem *reg; member
63 u32 reg; in orion_wdt_start() local
68 reg = readl(priv->reg + TIMER_CTRL); in orion_wdt_start()
70 writel(reg, priv->reg + TIMER_CTRL); in orion_wdt_start()
77 reg = readl(priv->reg + TIMER_A370_STATUS); in orion_wdt_start()
79 writel(reg, priv->reg + TIMER_A370_STATUS); in orion_wdt_start()
82 reg = readl(priv->reg + TIMER_CTRL); in orion_wdt_start()
84 writel(reg, priv->reg + TIMER_CTRL); in orion_wdt_start()
101 u32 reg; in orion_wdt_stop() local
113 reg = readl(priv->reg + TIMER_CTRL); in orion_wdt_stop()
[all …]
/u-boot/arch/mips/dts/
A Djr2_pcb111.dts81 reg = <0>;
84 reg = <1>;
87 reg = <2>;
90 reg = <3>;
93 reg = <4>;
96 reg = <5>;
99 reg = <6>;
102 reg = <7>;
105 reg = <8>;
108 reg = <9>;
[all …]
A Dluton_pcb090.dts63 reg = <0>;
66 reg = <1>;
69 reg = <2>;
72 reg = <3>;
75 reg = <4>;
78 reg = <5>;
81 reg = <6>;
84 reg = <7>;
87 reg = <8>;
90 reg = <9>;
[all …]
/u-boot/arch/arm/mach-imx/mx6/
A Dclock.c31 u32 reg; in enable_ocotp_clk() local
85 u32 reg; in enable_usboh3_clk() local
158 u32 reg; in enable_i2c_clk() local
198 u32 reg; in enable_spi_clk() local
207 reg |= mask; in enable_spi_clk()
1067 reg |= en; in enable_enet_pll()
1160 u32 reg; in hab_caam_clock_enable() local
1227 u32 reg; in enable_eim_clk() local
1348 int reg; in disable_ldb_di_clock_sources() local
1373 int reg; in enable_ldb_di_clock_sources() local
[all …]
/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_gen5.c347 u32 reg, clock; in cm_get_main_vco_clk_hz() local
362 u32 reg, clock = 0; in cm_get_per_vco_clk_hz() local
366 reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >> in cm_get_per_vco_clk_hz()
387 u32 reg, clock; in cm_get_mpu_clk_hz() local
393 clock /= (reg + 1); in cm_get_mpu_clk_hz()
405 reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >> in cm_get_sdram_clk_hz()
423 reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >> in cm_get_sdram_clk_hz()
436 reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >> in cm_get_l4_sp_clk_hz()
460 reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >> in cm_get_l4_sp_clk_hz()
473 reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >> in cm_get_mmc_controller_clk_hz()
[all …]
/u-boot/board/freescale/ls1043aqds/
A Dls1043aqds.c335 u8 reg; in board_retimer_init() local
363 reg = 0x0; in board_retimer_init()
371 reg = 0x0c; in board_retimer_init()
376 reg |= 0x4; in board_retimer_init()
396 reg = 0x0; in board_retimer_init()
398 reg = 0xb2; in board_retimer_init()
400 reg = 0x90; in board_retimer_init()
402 reg = 0xb3; in board_retimer_init()
410 reg = 0x0; in board_retimer_init()
443 reg = 0x0; in board_retimer_init()
[all …]
/u-boot/board/freescale/common/
A Dpfuze.c54 unsigned int reg; in pfuze_common_init() local
70 reg &= ~SW1x_STBY_MASK; in pfuze_common_init()
71 reg |= SW1x_0_975V; in pfuze_common_init()
77 reg |= SW1xCONF_DVSSPEED_4US; in pfuze_common_init()
82 reg &= ~SW1x_STBY_MASK; in pfuze_common_init()
83 reg |= SW1x_0_975V; in pfuze_common_init()
89 reg |= SW1xCONF_DVSSPEED_4US; in pfuze_common_init()
149 reg &= ~SW1x_STBY_MASK; in pfuze_common_init()
150 reg |= SW1x_0_975V; in pfuze_common_init()
161 reg &= ~SW1x_STBY_MASK; in pfuze_common_init()
[all …]
/u-boot/drivers/pci/
A Dpci-aardvark.c129 #define PCIE_CONF_REG(reg) ((reg) & 0xffc) argument
233 uint reg; in pcie_advk_check_pio_status() local
314 uint reg; in pcie_advk_read_config() local
356 offset, size, reg); in pcie_advk_read_config()
411 uint reg; in pcie_advk_write_config() local
520 u32 reg; in pcie_advk_setup_hw() local
566 reg |= SPEED_GEN_2; in pcie_advk_setup_hw()
571 reg &= ~LANE_CNT_MSK; in pcie_advk_setup_hw()
572 reg |= LANE_COUNT_1; in pcie_advk_setup_hw()
577 reg |= LINK_TRAINING_EN; in pcie_advk_setup_hw()
[all …]
/u-boot/drivers/clk/at91/
A Dclk-main.c36 void __iomem *reg; member
63 void __iomem *reg = main_rc->reg; in main_rc_enable() local
87 struct reg *reg = main_rc->reg; in main_rc_disable() local
121 main_rc->reg = reg; in at91_clk_main_rc()
144 void __iomem *reg = main->reg; in clk_main_osc_enable() local
171 void __iomem *reg = main->reg; in clk_main_osc_disable() local
207 main->reg = reg; in at91_clk_main_osc()
273 main->reg = reg; in at91_clk_rm9200_main()
305 void __iomem *reg = main->reg; in clk_sam9x5_main_enable() local
318 void __iomem *reg = main->reg; in clk_sam9x5_main_set_parent() local
[all …]
/u-boot/board/tbs/tbs2910/
A Dtbs2910.c97 int reg; in setup_display() local
127 reg |= BM_ANADIG_PLL_VIDEO_ENABLE; in setup_display()
128 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; in setup_display()
132 reg = readl(&ccm->CCGR3); in setup_display()
133 reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK; in setup_display()
134 writel(reg, &ccm->CCGR3); in setup_display()
137 reg = readl(&ccm->chsccdr); in setup_display()
144 writel(reg, &ccm->chsccdr); in setup_display()
147 reg = readl(&ccm->CCGR3); in setup_display()
148 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; in setup_display()
[all …]
/u-boot/arch/x86/cpu/quark/
A Dmsg_port.c18 u32 msg_port_read(u8 port, u32 reg) in msg_port_read() argument
23 reg & 0xffffff00); in msg_port_read()
24 msg_port_setup(MSG_OP_READ, port, reg); in msg_port_read()
34 reg & 0xffffff00); in msg_port_write()
35 msg_port_setup(MSG_OP_WRITE, port, reg); in msg_port_write()
38 u32 msg_port_alt_read(u8 port, u32 reg) in msg_port_alt_read() argument
43 reg & 0xffffff00); in msg_port_alt_read()
54 reg & 0xffffff00); in msg_port_alt_write()
58 u32 msg_port_io_read(u8 port, u32 reg) in msg_port_io_read() argument
63 reg & 0xffffff00); in msg_port_io_read()
[all …]
/u-boot/drivers/spi/
A Dcadence_qspi_apb.c183 unsigned int reg; in cadence_qspi_apb_controller_enable() local
191 unsigned int reg; in cadence_qspi_apb_controller_disable() local
199 unsigned int reg; in cadence_qspi_apb_dac_mode_enable() local
236 unsigned int reg; in cadence_qspi_apb_readdata_capture() local
260 unsigned int reg; in cadence_qspi_apb_config_baudrate_div() local
289 unsigned int reg; in cadence_qspi_apb_set_clk_mode() local
308 unsigned int reg; in cadence_qspi_apb_chipselect() local
382 unsigned reg; in cadence_qspi_apb_controller_init() local
585 u32 reg; in cadence_qspi_wait_for_data() local
589 if (reg) in cadence_qspi_wait_for_data()
[all …]
/u-boot/drivers/video/imx/
A Dipu_disp.c185 u32 reg; in ipu_di_data_wave_config() local
194 u32 reg; in ipu_di_data_pin_config() local
213 u32 reg; in ipu_di_sync_config() local
242 u32 reg; in ipu_dc_map_config() local
265 u32 reg; in ipu_dc_write_tmpl() local
268 reg = sync; in ipu_dc_write_tmpl()
283 u32 reg; in ipu_dc_link_event() local
384 u32 reg; in ipu_dp_csc_setup() local
534 u32 reg = 0; in ipu_dc_init() local
561 reg = 0x2; in ipu_dc_init()
[all …]
/u-boot/drivers/pinctrl/rockchip/
A Dpinctrl-rv1108.c20 .reg = 0x418,
26 .reg = 0x418,
32 .reg = 0x418,
38 .reg = 0x418,
44 .reg = 0x418,
50 .reg = 0x418,
56 .reg = 0x418,
62 .reg = 0x418,
68 .reg = 0x41c,
74 .reg = 0x41c,
[all …]
/u-boot/drivers/clk/imx/
A Dclk.h65 void __iomem *reg, u8 shift) in imx_clk_gate4() argument
69 reg, shift, 0x3, 0); in imx_clk_gate4()
78 reg, shift, 0x3, 0); in imx_clk_gate4_flags()
92 reg, shift, width, 0); in imx_clk_divider()
100 reg, shift, width, 0); in imx_clk_busy_divider()
108 reg, shift, width, 0); in imx_clk_divider2()
112 void __iomem *reg, u8 idx);
135 reg, shift, width, 0); in imx_clk_mux2_flags()
163 reg, shift, width, 0); in imx_clk_mux2()
167 void __iomem *reg, u8 shift) in imx_clk_gate() argument
[all …]
/u-boot/arch/arm/mach-sunxi/
A Dpmic_bus.c63 int pmic_bus_read(u8 reg, u8 *data) in pmic_bus_read() argument
73 return p2wi_read(reg, data); in pmic_bus_read()
77 return rsb_read(AXP223_RUNTIME_ADDR, reg, data); in pmic_bus_read()
82 int pmic_bus_write(u8 reg, u8 data) in pmic_bus_write() argument
92 return p2wi_write(reg, data); in pmic_bus_write()
101 int pmic_bus_setbits(u8 reg, u8 bits) in pmic_bus_setbits() argument
106 ret = pmic_bus_read(reg, &val); in pmic_bus_setbits()
114 return pmic_bus_write(reg, val); in pmic_bus_setbits()
117 int pmic_bus_clrbits(u8 reg, u8 bits) in pmic_bus_clrbits() argument
122 ret = pmic_bus_read(reg, &val); in pmic_bus_clrbits()
[all …]

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