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Searched refs:reg_offset (Results 1 – 25 of 31) sorted by relevance

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/u-boot/drivers/power/pmic/
A Dpmic_tps65910.c82 unsigned int reg_offset; in tps65910_voltage_update() local
86 reg_offset = TPS65910_VDD1_OP_REG; in tps65910_voltage_update()
88 reg_offset = TPS65910_VDD2_OP_REG; in tps65910_voltage_update()
91 ret = tps65910_read_reg(reg_offset, &buf); in tps65910_voltage_update()
97 ret = tps65910_write_reg(reg_offset, &buf); in tps65910_voltage_update()
102 ret = tps65910_read_reg(reg_offset, &buf); in tps65910_voltage_update()
109 ret = tps65910_write_reg(reg_offset, &buf); in tps65910_voltage_update()
113 ret = tps65910_read_reg(reg_offset, &buf); in tps65910_voltage_update()
/u-boot/arch/powerpc/include/asm/
A Dfsl_liodn.h14 unsigned long reg_offset[2]; member
20 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
26 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
28 .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
34 .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
44 unsigned long reg_offset; member
56 unsigned long reg_offset; member
73 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
80 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
87 .reg_offset = off + CONFIG_SYS_CCSRBAR, \
/u-boot/arch/arm/mach-omap2/am33xx/
A Dmux.c31 for (i = 0; mod_pin_mux[i].reg_offset != -1; i++) in configure_module_pin_mux()
32 MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset); in configure_module_pin_mux()
/u-boot/drivers/pinctrl/mvebu/
A Dpinctrl-mvebu.c101 int reg_offset; in mvebu_pinctrl_set_state() local
112 reg_offset = priv->reg_direction * 4 * in mvebu_pinctrl_set_state()
116 clrsetbits_le32(priv->base_reg + reg_offset, in mvebu_pinctrl_set_state()
158 int reg_offset; in mvebu_pinctrl_set_state_all() local
173 reg_offset = priv->reg_direction * 4 * in mvebu_pinctrl_set_state_all()
177 clrsetbits_le32(priv->base_reg + reg_offset, in mvebu_pinctrl_set_state_all()
/u-boot/board/siemens/pxm2/
A Dboard.c98 unsigned int reg_offset; in voltage_update() local
101 reg_offset = PMIC_VDD1_OP_REG; in voltage_update()
103 reg_offset = PMIC_VDD2_OP_REG; in voltage_update()
106 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
111 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
115 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
121 if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
124 if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) in voltage_update()
/u-boot/drivers/reset/
A Dreset-meson.c43 uint reg_offset = LEVEL_OFFSET + (bank << 2); in meson_reset_level() local
46 regmap_read(priv->regmap, reg_offset, &val); in meson_reset_level()
51 regmap_write(priv->regmap, reg_offset, val); in meson_reset_level()
A Dreset-rockchip.c110 int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number) in rockchip_reset_bind() argument
123 priv->reset_reg_offset = reg_offset; in rockchip_reset_bind()
/u-boot/arch/arm/include/asm/arch-ls102xa/
A Dls102xa_stream_id.h14 .reg_offset = off + CONFIG_SYS_IMMR, \
21 .reg_offset = off + CONFIG_SYS_IMMR, \
62 unsigned long reg_offset; member
/u-boot/drivers/pinctrl/broadcom/
A Dpinctrl-bcm283x.c36 int reg_offset; in bcm2835_gpio_set_func_id() local
39 reg_offset = BCM2835_GPIO_FSEL_BANK(gpio); in bcm2835_gpio_set_func_id()
42 clrsetbits_le32(&priv->base_reg[reg_offset], in bcm2835_gpio_set_func_id()
/u-boot/drivers/gpio/
A Dgpio-uniphier.c86 unsigned int bank, reg_offset; in uniphier_gpio_offset_read() local
90 reg_offset = uniphier_gpio_bank_to_reg(bank) + reg; in uniphier_gpio_offset_read()
92 return !!(readl(priv->regs + reg_offset) & mask); in uniphier_gpio_offset_read()
A Dzynq_gpio.c251 unsigned int reg_offset, bank_num, bank_pin_num; in zynq_gpio_set_value() local
262 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); in zynq_gpio_set_value()
264 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); in zynq_gpio_set_value()
275 writel(value, plat->base + reg_offset); in zynq_gpio_set_value()
/u-boot/arch/arm/include/asm/arch-am33xx/
A Dmux.h32 short reg_offset; member
/u-boot/arch/powerpc/cpu/mpc85xx/
A Dliodn.c33 unsigned long reg_off = tbl[i].reg_offset[0]; in set_srio_liodn()
37 reg_off = tbl[i].reg_offset[1]; in set_srio_liodn()
56 out_be32((volatile u32 *)(tbl[i].reg_offset), liodn); in set_liodn()
72 out_be32((volatile u32 *)(tbl[i].reg_offset), liodn); in set_fman_liodn()
164 out_be32((u32 *)(tbl[i].reg_offset), tbl[i].id[0]); in set_rman_liodn()
/u-boot/board/freescale/common/
A Dls102xa_stream_id.c33 out_le32((u32 *)(tbl[i].reg_offset), liodn); in ls1021x_config_caam_stream_id()
/u-boot/drivers/serial/
A Dserial_intel_mid.c31 writel(value, addr + plat->reg_offset); in mid_writel()
A Dns16550.c166 addr = (unsigned char *)plat->base + offset + plat->reg_offset; in ns16550_writeb()
180 addr = (unsigned char *)plat->base + offset + plat->reg_offset; in ns16550_readb()
480 info->reg_offset = plat->reg_offset; in ns16550_serial_getinfo()
550 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); in ns16550_serial_of_to_plat()
A Dserial_omap.c116 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); in omap_serial_of_to_plat()
/u-boot/drivers/spi/
A Dmtk_snor.c388 int reg_offset = MTK_NOR_REG_PRGDATA_MAX; in mtk_snor_cmd_program() local
417 for (i = 0; i < tx_len; i++, reg_offset--) in mtk_snor_cmd_program()
418 writeb(txbuf[i], priv->base + MTK_NOR_REG_PRGDATA(reg_offset)); in mtk_snor_cmd_program()
426 reg_offset = op->data.nbytes - 1; in mtk_snor_cmd_program()
427 for (i = 0; i < op->data.nbytes; i++, reg_offset--) { in mtk_snor_cmd_program()
428 reg = priv->base + MTK_NOR_REG_SHIFT(reg_offset); in mtk_snor_cmd_program()
/u-boot/drivers/net/
A Dsh_eth.h657 const u16 *reg_offset = sh_eth_offset_gigabit; in sh_eth_reg_addr() local
659 const u16 *reg_offset = sh_eth_offset_fast_sh4; in sh_eth_reg_addr()
661 const u16 *reg_offset = sh_eth_offset_rz; in sh_eth_reg_addr()
665 return (unsigned long)port->iobase + reg_offset[enum_index]; in sh_eth_reg_addr()
A Dmvgbe.c351 u32 reg_offset; in port_uc_addr() local
358 reg_offset = uc_nibble % 4; in port_uc_addr()
367 unicast_reg &= (0xFF << (8 * reg_offset)); in port_uc_addr()
373 unicast_reg &= (0xFF << (8 * reg_offset)); in port_uc_addr()
374 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset)); in port_uc_addr()
/u-boot/drivers/pwm/
A Dpwm-meson.c52 u8 reg_offset; member
59 .reg_offset = REG_PWM_A,
66 .reg_offset = REG_PWM_B,
209 writel(value, priv->base + channel_data->reg_offset); in meson_pwm_set_enable()
/u-boot/drivers/ddr/marvell/a38x/
A Dddr3_training_ip_engine.c703 u32 reg_offset, pup_cnt, start_pup, end_pup, start_reg, end_reg; in ddr3_tip_read_training_result() local
789 for (reg_offset = start_reg; reg_offset <= end_reg; in ddr3_tip_read_training_result()
790 reg_offset++) { in ddr3_tip_read_training_result()
797 reg_addr[reg_offset], in ddr3_tip_read_training_result()
804 [reg_offset] = in ddr3_tip_read_training_result()
809 [reg_offset] = in ddr3_tip_read_training_result()
815 interface_train_res[reg_offset] in ddr3_tip_read_training_result()
822 reg_offset, in ddr3_tip_read_training_result()
824 [reg_offset], in ddr3_tip_read_training_result()
826 [reg_offset])); in ddr3_tip_read_training_result()
/u-boot/arch/x86/cpu/apollolake/
A Duart.c110 ns.reg_offset = 0; in apl_ns16550_of_to_plat()
/u-boot/arch/arm/include/asm/arch-rockchip/
A Dclock.h173 int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
/u-boot/include/
A Dns16550.h77 int reg_offset; member

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