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Searched refs:reg_read (Results 1 – 24 of 24) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_dfs.c133 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
149 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
207 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
226 reg = reg_read(CPU_PLL_CNTRL0); in ddr3_dfs_high_2_low()
233 reg = reg_read(CPU_PLL_CNTRL0); in ddr3_dfs_high_2_low()
362 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
454 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
789 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_low_2_high()
805 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_low_2_high()
810 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_low_2_high()
[all …]
A Dddr3_write_leveling.c77 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_write_leveling_hw()
101 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_write_leveling_hw()
682 reg = reg_read(REG_DDR3_MR1_ADDR) & in ddr3_write_leveling_sw()
739 ((reg_read in ddr3_write_leveling_sw()
747 reg = reg_read(REG_DDR3_MR1_ADDR) & in ddr3_write_leveling_sw()
803 reg = reg_read(REG_DDR3_MR1_ADDR) & in ddr3_write_leveling_sw()
840 reg = reg_read(REG_DDR3_MR1_ADDR) & in ddr3_write_leveling_sw()
917 reg = reg_read(REG_DDR3_MR1_ADDR) & in ddr3_write_leveling_sw_reg_dimm()
973 ((reg_read in ddr3_write_leveling_sw_reg_dimm()
984 reg = reg_read(REG_DDR3_MR1_ADDR) & in ddr3_write_leveling_sw_reg_dimm()
[all …]
A Dddr3_init.c73 printf("0x%08x = 0x%08x\n", reg, reg_read(reg)); in debug_print_reg()
450 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & in ddr3_init_main()
471 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_init_main()
493 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_init_main()
510 reg = reg_read(REG_TRAINING_DEBUG_3_ADDR); in ddr3_init_main()
641 reg = reg_read(REG_SDRAM_CONFIG_ADDR) & in ddr3_init_main()
652 reg = reg_read(REG_BOOTROM_ROUTINE_ADDR); in ddr3_init_main()
659 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_init_main()
731 reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR); in ddr3_get_fab_opt()
818 reg = reg_read(reg_addr); in ddr3_get_static_mc_value()
[all …]
A Dddr3_hw_training.c107 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
116 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
125 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_hw_training()
131 reg = reg_read(REG_DDR3_MR0_ADDR) >> 2; in ddr3_hw_training()
133 reg = reg_read(REG_DDR3_MR0_CS_ADDR) >> 2; in ddr3_hw_training()
645 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_load_patterns()
681 if (reg_read(REG_DRAM_TRAINING_ADDR) & in ddr3_load_patterns()
925 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_training_suspend_resume()
941 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_training_suspend_resume()
1076 reg = reg_read(REG_DUNIT_ODT_CTRL_ADDR); in ddr3_odt_activate()
[all …]
A Dddr3_read_leveling.c79 reg = reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) | in ddr3_read_leveling_hw()
90 if (reg_read(REG_DRAM_TRAINING_SHADOW_ADDR) & in ddr3_read_leveling_hw()
152 reg_read(REG_READ_DATA_READY_DELAYS_ADDR) & in ddr3_read_leveling_hw()
189 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_read_leveling_sw()
208 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_read_leveling_sw()
299 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_read_leveling_sw()
310 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_read_leveling_sw()
319 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_read_leveling_sw()
446 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_read_leveling_single_cs_rl_mode()
700 add = reg_read(REG_TRAINING_DEBUG_2_ADDR); in ddr3_read_leveling_single_cs_rl_mode()
[all …]
A Dxor.c28 xor_regs_ctrl_backup = reg_read(XOR_WINDOW_CTRL_REG(0, 0)); in mv_sys_xor_init()
30 xor_regs_base_backup[ui] = reg_read(XOR_BASE_ADDR_REG(0, ui)); in mv_sys_xor_init()
32 xor_regs_mask_backup[ui] = reg_read(XOR_SIZE_MASK_REG(0, ui)); in mv_sys_xor_init()
146 val = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) in mv_xor_ctrl_set()
172 tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_mem_init()
262 tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_transfer()
352 state = reg_read(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_state_get()
A Dddr3_pbs.c109 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_pbs_tx()
160 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_pbs_tx()
286 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_pbs_tx()
382 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_pbs_tx()
387 reg = reg_read(REG_DRAM_TRAINING_1_ADDR) | in ddr3_pbs_tx()
552 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_pbs_rx()
602 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_pbs_rx()
674 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_pbs_rx()
692 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_pbs_rx()
894 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_pbs_rx()
[all …]
A Dddr3_sdram.c53 while (!(reg_read(XOR_CAUSE_REG(XOR_UNIT(chan))) & in xor_waiton_eng()
564 reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR) & in ddr3_flush_l1_line()
641 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_reset_phy_read_fifo()
648 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_reset_phy_read_fifo()
657 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_reset_phy_read_fifo()
661 reg = reg_read(REG_DRAM_TRAINING_ADDR); in ddr3_reset_phy_read_fifo()
A Dddr3_dqs.c139 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_dqs_centralization_rx()
159 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_dqs_centralization_rx()
188 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_dqs_centralization_rx()
194 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_dqs_centralization_rx()
199 reg = reg_read(REG_DRAM_TRAINING_1_ADDR) | in ddr3_dqs_centralization_rx()
221 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) | in ddr3_dqs_centralization_tx()
239 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_dqs_centralization_tx()
268 reg = reg_read(REG_DRAM_TRAINING_2_ADDR) & in ddr3_dqs_centralization_tx()
274 reg = reg_read(REG_DRAM_TRAINING_2_ADDR); in ddr3_dqs_centralization_tx()
279 reg = reg_read(REG_DRAM_TRAINING_1_ADDR) | in ddr3_dqs_centralization_tx()
A Dddr3_spd.c690 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
697 reg = (reg_read(REG_DDR3_MR0_ADDR) >> 2);
890 reg |= (reg_read(REG_SDRAM_ADDRESS_CTRL_ADDR) & 0xF0FFFF);
963 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
997 reg = reg_read(REG_DRAM_MAIN_PADS_CAL_ADDR);
1004 reg = reg_read(REG_DRAM_MAIN_PADS_CAL_ADDR);
1083 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
1197 reg = reg_read(REG_REGISTERED_DRAM_CTRL_ADDR);
1206 reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &
1230 reg = reg_read(REG_SDRAM_OPERATION_ADDR) &
A Dddr3_init.h127 static inline u32 reg_read(u32 addr) in reg_read() function
/u-boot/arch/arm/mach-mvebu/serdes/a38x/
A Dsys_env_lib.c46 value = (reg_read(DEVICE_SAMPLE_AT_RESET1_REG) >> 15) & 0x1; in mv_board_tclk_get()
107 reg = reg_read(MPP_CONTROL_REG(MPP_REG_NUM(gpio))); in sys_env_suspend_wakeup_check()
113 reg = reg_read(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio))); in sys_env_suspend_wakeup_check()
121 reg = reg_read(GPP_DATA_IN_REG(GPP_REG_NUM(gpio))); in sys_env_suspend_wakeup_check()
177 u32 default_ctrl_id, ctrl_id = reg_read(DEV_ID_REG); in sys_env_model_get()
211 g_dev_id = reg_read(DEVICE_SAMPLE_AT_RESET1_REG); in sys_env_device_id_get()
238 value = reg_read(DEV_VERSION_ID_REG); in sys_env_device_rev_get()
263 sar_freq = reg_read(DEVICE_SAMPLE_AT_RESET1_REG); in mv_avs_init()
270 u32 avs_reg_data = reg_read(AVS_ENABLED_CONTROL); in mv_avs_init()
A Dctrl_pex.c46 tmp = reg_read(PEX_CAPABILITIES_REG(pex_idx)); in hws_pex_config()
52 tmp = reg_read(SOC_CTRL_REG); in hws_pex_config()
114 tmp = reg_read(PEX_DBG_STATUS_REG(pex_idx)); in hws_pex_config()
125 temp_pex_reg = reg_read((PEX_CFG_DIRECT_ACCESS in hws_pex_config()
131 temp_reg = (reg_read(PEX_CFG_DIRECT_ACCESS( in hws_pex_config()
181 tmp = reg_read(PEX_CTRL_REG(pex_idx)); in hws_pex_config()
217 dev_id = reg_read(PEX_CFG_DIRECT_ACCESS in hws_pex_config()
241 pex_status = reg_read(PEX_STATUS_REG(pex_if)); in pex_local_bus_num_set()
256 pex_status = reg_read(PEX_STATUS_REG(pex_if)); in pex_local_dev_num_set()
294 pex_status = reg_read(PEX_STATUS_REG(pex_if)); in pex_config_read()
[all …]
A Dseq_exec.c55 reg_data = reg_read(reg_addr); in write_op_execute()
114 reg_data = reg_read(reg_addr) & mask; in poll_op_execute()
A Dhigh_speed_env_spec.c1400 data = reg_read(CORE_PLL_CONFIG_REG); in hws_pre_serdes_init_config()
1458 data = reg_read(reg_addr); in serdes_polarity_config()
1609 reg_satr1 = reg_read(DEVICE_SAMPLE_AT_RESET1_REG); in hws_serdes_pex_ref_clock_satr_get()
1719 reg_data = reg_read(SOC_CONTROL_REG1); in serdes_power_up_ctrl()
1727 reg_read(((PEX_IF_REGS_BASE(pex_idx)) + in serdes_power_up_ctrl()
1738 reg_read(((PEX_IF_REGS_BASE(pex_idx)) + in serdes_power_up_ctrl()
1746 reg_read(((PEX_IF_REGS_BASE(pex_idx)) + in serdes_power_up_ctrl()
1858 reg_data = reg_read(GBE_CONFIGURATION_REG); in serdes_power_up_ctrl()
2086 reg_data = reg_read(POWER_AND_PLL_CTRL_REG + in hws_ref_clock_set()
2095 reg_data = reg_read(GLOBAL_PM_CTRL + in hws_ref_clock_set()
[all …]
/u-boot/arch/arm/mach-mvebu/serdes/axp/
A Dhigh_speed_env_lib.c175 sar = reg_read(MPP_SAMPLE_AT_RESET(0)); in board_cpu_freq_get()
285 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & in serdes_phy_config()
312 tmp2 = reg_read(CPU_AVS_CONTROL0_REG); in serdes_phy_config()
503 tmp = reg_read(QSGMII_CONTROL_1_REG); in serdes_phy_config()
633 tmp = reg_read(SOC_CTRL_REG); in serdes_phy_config()
704 tmp = reg_read(GEN_PURP_RES_2_REG); in serdes_phy_config()
1036 reg_read(PEX_DBG_CTRL_REG in serdes_phy_config()
1193 tmp = reg_read(SOC_CTRL_REG); in serdes_phy_config()
1280 (reg_read in serdes_phy_config()
1327 reg_read in serdes_phy_config()
[all …]
/u-boot/drivers/ddr/marvell/a38x/
A Dmv_ddr_sys_env_lib.c68 reg = reg_read(MPP_CONTROL_REG(MPP_REG_NUM(gpio))); in mv_ddr_sys_env_suspend_wakeup_check()
74 reg = reg_read(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio))); in mv_ddr_sys_env_suspend_wakeup_check()
82 reg = reg_read(GPP_DATA_IN_REG(GPP_REG_NUM(gpio))); in mv_ddr_sys_env_suspend_wakeup_check()
97 return reg_read(DDR3_RANK_CTRL_REG) & in mv_ddr_sys_env_get_cs_ena_from_reg()
A Dmv_ddr_plat.c199 reg = reg_read(TSEN_CONTROL_LSB_REG); in ddr3_ctrl_get_junc_temp()
212 reg = reg_read(TSEN_STATUS_REG); in ddr3_ctrl_get_junc_temp()
244 *data = reg_read(addr) & mask; in dunit_read()
369 reg = reg_read(DUAL_DUNIT_CFG_REG); in ddr3_tip_a38x_select_ddr_controller()
394 reg = (reg_read(REG_DEVICE_SAR1_ADDR) >> in mv_ddr_sar_freq_get()
488 reg = (reg_read(REG_DEVICE_SAR1_ADDR) >> in ddr3_tip_a38x_get_medium_freq()
747 sar_val = (reg_read(REG_DEVICE_SAR1_ADDR) >> in ddr3_tip_a38x_set_divider()
965 data = reg_read(SDRAM_ADDR_CTRL_REG); in ddr3_get_device_size()
1244 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) & in mv_ddr_pre_training_soc_config()
1251 reg_val = reg_read(TRAINING_DBG_3_REG); in mv_ddr_pre_training_soc_config()
[all …]
A Dxor.c26 ui_xor_regs_ctrl_backup = reg_read(XOR_WINDOW_CTRL_REG(0, 0)); in mv_sys_xor_init()
29 reg_read(XOR_BASE_ADDR_REG(0, ui)); in mv_sys_xor_init()
32 reg_read(XOR_SIZE_MASK_REG(0, ui)); in mv_sys_xor_init()
156 old_value = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) & in mv_xor_ctrl_set()
185 temp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_mem_init()
253 state = reg_read(XOR_ACTIVATION_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_state_get()
415 temp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_transfer()
A Dddr_ml_wrapper.h131 static inline u32 reg_read(u32 addr) in reg_read() function
/u-boot/arch/arm/mach-mvebu/
A Ddram.c125 xor_ctrl_save = reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, in mv_xor_init2()
127 xor_base_save = reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, in mv_xor_init2()
129 xor_mask_save = reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, in mv_xor_init2()
180 temp = reg_read(REG_SDRAM_CONFIG_ADDR); in dram_ecc_scrubbing()
210 temp = reg_read(REG_SDRAM_CONFIG_ADDR); in dram_ecc_scrubbing()
217 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS)) in ecc_enabled()
228 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS)) in bus_width()
246 int val = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in cycle_mode()
/u-boot/drivers/spi/
A Dmxc_spi.c116 #define reg_read readl macro
288 reg_config = reg_read(&regs->cfg); in spi_cfg_mxc()
389 status = reg_read(&regs->stat); in spi_xchg_single()
396 status = reg_read(&regs->stat); in spi_xchg_single()
407 data = reg_read(&regs->rxdata); in spi_xchg_single()
420 tmp = reg_read(&regs->rxdata); in spi_xchg_single()
/u-boot/board/Synology/ds414/
A Dds414.c169 pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG); in board_init()
A Dcmd_syno.c158 u32 pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG); in do_syno_clk_gate()

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