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Searched refs:rl_val (Results 1 – 3 of 3) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_read_leveling.c118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
354 info->rl_val[cs][idx][C]++; in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
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A Dddr3_hw_training.h260 u32 rl_val[MAX_CS][MAX_PUP_NUM][7]; member
/u-boot/drivers/ddr/marvell/a38x/
A Dddr3_training_leveling.c1688 u32 rl_val, rl_min_val[MAX_CS_NUM], rl_max_val[MAX_CS_NUM]; in mv_ddr_rl_dqs_burst() local
1740 rl_val = 0; in mv_ddr_rl_dqs_burst()
1757 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1762 0, DDR_PHY_DATA, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()
1938 rl_val = ((rl_adll_val & RL_REF_DLY_MASK) << RL_REF_DLY_OFFS) | in mv_ddr_rl_dqs_burst()
1941 subphy_id, subphy_type, RL_PHY_REG(effective_cs), rl_val); in mv_ddr_rl_dqs_burst()

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