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Searched refs:setbits_be16 (Results 1 – 25 of 27) sorted by relevance

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/u-boot/arch/powerpc/include/asm/
A Diopin_8xx.h35 setbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_high()
43 setbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_high()
47 setbits_be16(datp, 1 << (15 - iopin->pin)); in iopin_set_high()
129 setbits_be16(dirp, 1 << (15 - iopin->pin)); in iopin_set_out()
137 setbits_be16(dirp, 1 << (15 - iopin->pin)); in iopin_set_out()
141 setbits_be16(dirp, 1 << (15 - iopin->pin)); in iopin_set_out()
223 setbits_be16(odrp, 1 << (15 - iopin->pin)); in iopin_set_odr()
227 setbits_be16(odrp, 1 << (31 - iopin->pin)); in iopin_set_odr()
285 setbits_be16(parp, 1 << (15 - iopin->pin)); in iopin_set_ded()
293 setbits_be16(parp, 1 << (15 - iopin->pin)); in iopin_set_ded()
[all …]
A Dio.h277 #define setbits_be16(addr, set) setbits(be16, addr, set) macro
/u-boot/drivers/serial/
A Dserial_mpc8xx.c149 setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP); in serial_mpc8xx_probe()
150 setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY | BD_SC_WRAP); in serial_mpc8xx_probe()
168 setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); in serial_mpc8xx_probe()
187 setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY); in serial_mpc8xx_putc()
219 setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY); in serial_mpc8xx_getc()
/u-boot/drivers/net/
A Dmpc8xx_fec.c196 setbits_be16(&rtx->txbd[txIdx].cbd_sc, in fec_send()
369 setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080); in fec_pin_init()
380 setbits_be16(&immr->im_ioport.iop_papar, 0xf830); in fec_pin_init()
381 setbits_be16(&immr->im_ioport.iop_padir, 0x0830); in fec_pin_init()
387 setbits_be16(&immr->im_ioport.iop_pcpar, 0x000c); in fec_pin_init()
399 setbits_be16(&immr->im_ioport.iop_papar, 0x1000); in fec_pin_init()
402 setbits_be16(&immr->im_ioport.iop_papar, 0xe810); in fec_pin_init()
403 setbits_be16(&immr->im_ioport.iop_padir, 0x0810); in fec_pin_init()
578 setbits_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc, BD_ENET_RX_WRAP); in fec_init()
590 setbits_be16(&rtx->txbd[TX_BUF_CNT - 1].cbd_sc, BD_ENET_TX_WRAP); in fec_init()
/u-boot/arch/m68k/cpu/mcf523x/
A Dcpu_init.c135 setbits_be16(&gpio->par_uart, in uart_port_conf()
141 setbits_be16(&gpio->par_uart, in uart_port_conf()
148 setbits_be16(&gpio->par_uart, in uart_port_conf()
A Dcpu.c83 setbits_be16(&wdp->cr, WTM_WCR_HALTED); in watchdog_disable()
/u-boot/board/freescale/m54455evb/
A Dm54455evb.c105 setbits_be16(&gpio->par_feci2c, tmp); in ide_preinit()
107 setbits_be16(&gpio->par_ata, in ide_preinit()
112 setbits_be16(&gpio->par_pci, in ide_preinit()
/u-boot/arch/m68k/cpu/mcf52x2/
A Dcpu_init.c132 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); in uart_port_conf()
136 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD); in uart_port_conf()
499 setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK); in uart_port_conf()
503 setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK); in uart_port_conf()
507 setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK); in uart_port_conf()
524 setbits_be16(&gpio->par_feci2c, 0x0f00); in fecpin_setclear()
527 setbits_be16(&gpio->par_feci2c, 0x00a0); in fecpin_setclear()
/u-boot/arch/m68k/cpu/mcf5227x/
A Dcpu_init.c136 setbits_be16(&gpio->par_uart, in uart_port_conf()
142 setbits_be16(&gpio->par_uart, in uart_port_conf()
A Dspeed.c49 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_enter_limp()
/u-boot/arch/m68k/cpu/mcf547x_8x/
A Dcpu_init.c139 setbits_be16(&gpio->par_feci2cirq, 0xf000); in fecpin_setclear()
141 setbits_be16(&gpio->par_feci2cirq, 0x0fc0); in fecpin_setclear()
/u-boot/arch/m68k/cpu/mcf532x/
A Dcpu_init.c114 setbits_be16(&ccm->misccr, CCM_MISCCR_FECM); in cpu_init_r()
312 setbits_be16(&gpio->par_uart, in uart_port_conf()
318 setbits_be16(&gpio->par_uart, in uart_port_conf()
332 setbits_be16(&gpio->par_ssi, in uart_port_conf()
A Dcpu.c122 setbits_be16(&wdp->cr, WTM_WCR_HALTED); in watchdog_disable()
A Dspeed.c107 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_limp()
/u-boot/board/cssi/MCR3000/
A Dnand.c55 setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00); in board_nand_init()
/u-boot/arch/m68k/cpu/mcf5445x/
A Dcpu_init.c384 setbits_be16(&gpio->par_ssi, in uart_port_conf()
418 setbits_be16(&gpio->par_feci2c, in fecpin_setclear()
422 setbits_be16(&gpio->par_feci2c, in fecpin_setclear()
426 setbits_be16(&gpio->par_feci2c, in fecpin_setclear()
A Dspeed.c51 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_enter_limp()
106 setbits_be16(&ccm->misccr2, 0x02); in setup_5441x_clocks()
/u-boot/board/freescale/m54418twr/
A Dm54418twr.c58 setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK); in dram_init()
/u-boot/arch/sandbox/include/asm/
A Dio.h110 #define setbits_be16(addr, set) setbits(be16, addr, set) macro
174 #define setbits_be16(addr, set) setbits(be16, addr, set) macro
/u-boot/arch/nios2/include/asm/
A Dio.h159 #define setbits_be16(addr, set) setbits(be16, addr, set) macro
/u-boot/arch/arc/include/asm/
A Dio.h241 #define setbits_be16(addr, set) setbits(be16, addr, set) macro
/u-boot/arch/m68k/include/asm/
A Dio.h236 #define setbits_be16(addr, set) setbits(be16, addr, set) macro
/u-boot/arch/sh/include/asm/
A Dio.h223 #define setbits_be16(addr, set) setbits(be16, addr, set) macro
/u-boot/arch/x86/include/asm/
A Dio.h120 #define setbits_be16(addr, set) setbits(be16, addr, set) macro
/u-boot/arch/nds32/include/asm/
A Dio.h201 #define setbits_be16(addr, set) setbits(be16, addr, set) macro

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