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Searched refs:setbits_le32 (Results 1 – 25 of 349) sorted by relevance

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/u-boot/drivers/video/sunxi/
A Dsunxi_dw_hdmi.c72 setbits_le32(&phy->ctrl, BIT(0)); in sunxi_dw_hdmi_phy_init()
74 setbits_le32(&phy->ctrl, BIT(16)); in sunxi_dw_hdmi_phy_init()
75 setbits_le32(&phy->ctrl, BIT(1)); in sunxi_dw_hdmi_phy_init()
77 setbits_le32(&phy->ctrl, BIT(2)); in sunxi_dw_hdmi_phy_init()
79 setbits_le32(&phy->ctrl, BIT(3)); in sunxi_dw_hdmi_phy_init()
84 setbits_le32(&phy->ctrl, 7 << 4); in sunxi_dw_hdmi_phy_init()
96 setbits_le32(&phy->ctrl, BIT(7)); in sunxi_dw_hdmi_phy_init()
106 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_init()
178 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
192 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
[all …]
A Dsunxi_display.c112 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); in sunxi_hdmi_hpd_detect()
115 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); in sunxi_hdmi_hpd_detect()
167 setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START); in sunxi_hdmi_ddc_do_command()
231 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE); in sunxi_hdmi_edid_get_mode()
360 setbits_le32(&de_fe->enable, SUNXI_DE_FE_ENABLE_EN); in sunxi_frontend_init()
466 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE); in sunxi_composer_init()
499 setbits_le32(&de_be->mode, in sunxi_composer_mode_set()
522 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START); in sunxi_composer_enable()
540 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0); in sunxi_lcdc_init()
545 setbits_le32(&ccm->lvds_clk_cfg, CCM_LVDS_CTRL_RST); in sunxi_lcdc_init()
[all …]
A Dlcdc.c48 setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE); in lcdc_enable()
51 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0); in lcdc_enable()
54 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB); in lcdc_enable()
56 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC); in lcdc_enable()
58 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7)); in lcdc_enable()
60 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf)); in lcdc_enable()
62 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); in lcdc_enable()
64 setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1); in lcdc_enable()
66 setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2); in lcdc_enable()
67 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); in lcdc_enable()
[all …]
/u-boot/arch/x86/cpu/ivybridge/
A Dlpc.c262 setbits_le32(RCB_REG(0x228c), 1 << 0); in cpt_pm_init()
272 setbits_le32(RCB_REG(0x3344), 1 << 1); in cpt_pm_init()
296 setbits_le32(RCB_REG(0x21b0), 0xf); in cpt_pm_init()
304 setbits_le32(RCB_REG(0x2238), 1 << 0); in ppt_pm_init()
305 setbits_le32(RCB_REG(0x228c), 1 << 0); in ppt_pm_init()
335 setbits_le32(RCB_REG(0x3a88), 1 << 0); in ppt_pm_init()
341 setbits_le32(RCB_REG(0x21b0), 0xf); in ppt_pm_init()
355 setbits_le32(RCB_REG(0x2234), 0xf); in enable_clock_gating()
381 setbits_le32(RCB_REG(0x38c0), 0x7); in enable_clock_gating()
383 setbits_le32(RCB_REG(0x3564), 0x3); in enable_clock_gating()
[all …]
/u-boot/arch/x86/cpu/broadwell/
A Dpch.c65 setbits_le32(RCB_REG(GCS), 1 << 5); in broadwell_pch_early_init()
103 setbits_le32(RCB_REG(0x3310), 0x0000002f); in pch_misc_init()
350 setbits_le32(RCB_REG(DEEP_SX_CONFIG), in pch_init_deep_sx()
368 setbits_le32(RCB_REG(0x33e4), 0x1); in pch_pm_init()
375 setbits_le32(RCB_REG(0x2b1c), 1 << 29); in pch_pm_init()
386 setbits_le32(RCB_REG(0x2234), 0xf); in pch_cg_init()
409 setbits_le32(RCB_REG(0x2614), 1 << 26); in pch_cg_init()
438 setbits_le32(RCB_REG(0x3434), 0x7); in pch_cg_init()
441 setbits_le32(RCB_REG(0x38c0), 0x3c07); in pch_cg_init()
511 setbits_le32(RCB_REG(ACPIIRQEN), in serialio_init_once()
[all …]
/u-boot/drivers/usb/host/
A Dutmi-armada100.c25 setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP); in utmi_phy_init()
27 setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP); in utmi_phy_init()
30 setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER); in utmi_phy_init()
32 setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL); in utmi_phy_init()
42 setbits_le32(&phy_regs->utmi_pll, VCOCAL_START); in utmi_phy_init()
47 setbits_le32(&phy_regs->utmi_tx, RCAL_START); in utmi_phy_init()
72 setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M); in utmi_init()
A Dehci-vf.c102 setbits_le32(usb_cmd, UCMD_RESET); in usb_phy_enable()
128 setbits_le32(ctrl, UCTRL_OVER_CUR_POL); in usb_oc_config()
129 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); in usb_oc_config()
185 setbits_le32(&ehci->usbmode, CM_DEVICE); in ehci_hcd_init()
187 setbits_le32(&ehci->portsc, USB_EN); in ehci_hcd_init()
189 setbits_le32(&ehci->usbmode, CM_HOST); in ehci_hcd_init()
191 setbits_le32(&ehci->portsc, USB_EN); in ehci_hcd_init()
285 setbits_le32(&ehci->usbmode, CM_HOST); in vf_init_after_reset()
287 setbits_le32(&ehci->portsc, USB_EN); in vf_init_after_reset()
329 setbits_le32(&ehci->usbmode, CM_HOST); in ehci_usb_probe()
[all …]
A Dohci-lpc32xx.c127 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN); in isp1301_configure()
139 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN1); in usbpll_setup()
142 setbits_le32(&clk_pwr->usb_ctrl, in usbpll_setup()
144 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01)); in usbpll_setup()
145 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP); in usbpll_setup()
153 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN2); in usbpll_setup()
177 setbits_le32(&clk_pwr->usb_ctrl, in usb_cpu_init()
196 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBHSTND_EN); in usb_cpu_init()
208 setbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN); in usb_cpu_init()
A Dehci-exynos.c101 setbits_le32(&usb->usbphyctrl0, in exynos5_setup_usb_phy()
126 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); in exynos5_setup_usb_phy()
127 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); in exynos5_setup_usb_phy()
140 setbits_le32(&usb->ehcictrl, in exynos5_setup_usb_phy()
155 setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST)); in exynos4412_setup_usb_phy()
179 setbits_le32(&usb->usbphyctrl0, in exynos5_reset_usb_phy()
192 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); in exynos5_reset_usb_phy()
193 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); in exynos5_reset_usb_phy()
198 setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 | in exynos4412_reset_usb_phy()
/u-boot/drivers/video/
A Dbroadwell_igd.c87 setbits_le32(regs + 0xa248, 0x00000016); in haswell_early_init()
109 setbits_le32(regs + 0xa090, 0x00000000); in haswell_early_init()
110 setbits_le32(regs + 0xa098, 0x03e80000); in haswell_early_init()
111 setbits_le32(regs + 0xa09c, 0x00280000); in haswell_early_init()
112 setbits_le32(regs + 0xa0a8, 0x0001e848); in haswell_early_init()
113 setbits_le32(regs + 0xa0ac, 0x00000019); in haswell_early_init()
122 setbits_le32(regs + 0xa0b0, 0x00000000); in haswell_early_init()
123 setbits_le32(regs + 0xa0b4, 0x000003e8); in haswell_early_init()
174 setbits_le32(regs + 0x0a004, (1 << 4)); in haswell_late_init()
175 setbits_le32(regs + 0x0a080, (1 << 2)); in haswell_late_init()
[all …]
/u-boot/arch/arm/mach-exynos/
A Dpower.c46 setbits_le32(&power->usbhost_phy_control, in exynos5_set_usbhost_phy_ctrl()
62 setbits_le32(&power->usbhost_phy_control, in exynos4412_set_usbhost_phy_ctrl()
64 setbits_le32(&power->hsic1_phy_control, in exynos4412_set_usbhost_phy_ctrl()
66 setbits_le32(&power->hsic2_phy_control, in exynos4412_set_usbhost_phy_ctrl()
95 setbits_le32(&power->usbdrd_phy_control, in exynos5_set_usbdrd_phy_ctrl()
111 setbits_le32(&power->usbdev_phy_control, in exynos5420_set_usbdev_phy_ctrl()
113 setbits_le32(&power->usbdev1_phy_control, in exynos5420_set_usbdev_phy_ctrl()
161 setbits_le32(&power->ps_hold_control, in exynos5_set_ps_hold_ctrl()
202 setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP); in set_hw_thermal_trip()
/u-boot/arch/arm/mach-omap2/omap3/
A Dclock.c695 setbits_le32(&prcm_base->clksel_per, 0x000000FF); in prcm_init()
696 setbits_le32(&prcm_base->clksel_wkup, 1); in prcm_init()
709 setbits_le32(&prcm_base->iclken_usbhost, 1); in ehci_clocks_enable()
748 setbits_le32(&prcm_base->fclken_per, 0x00000800); in per_clocks_enable()
749 setbits_le32(&prcm_base->iclken_per, 0x00000800); in per_clocks_enable()
753 setbits_le32(&prcm_base->fclken_per, 0x00002000); in per_clocks_enable()
754 setbits_le32(&prcm_base->iclken_per, 0x00002000); in per_clocks_enable()
757 setbits_le32(&prcm_base->fclken_per, 0x00004000); in per_clocks_enable()
758 setbits_le32(&prcm_base->iclken_per, 0x00004000); in per_clocks_enable()
761 setbits_le32(&prcm_base->fclken_per, 0x00008000); in per_clocks_enable()
[all …]
/u-boot/arch/arm/mach-davinci/
A Dda850_lowlevel.c62 setbits_le32(&reg->pllctl, in da850_pll_init()
70 setbits_le32(&reg->pllctl, PLLCTL_PLLDIS); in da850_pll_init()
125 setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT); in da850_pll_init()
138 setbits_le32(&reg->pllctl, PLLCTL_PLLRST); in da850_pll_init()
147 setbits_le32(&reg->pllctl, PLLCTL_PLLEN); in da850_pll_init()
175 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); in da850_ddr_setup()
177 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); in da850_ddr_setup()
184 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); in da850_ddr_setup()
187 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); in da850_ddr_setup()
197 setbits_le32(&davinci_syscfg1_regs->ddr_slew, in da850_ddr_setup()
[all …]
/u-boot/arch/arm/mach-omap2/
A Dabb.c55 setbits_le32(setup, in abb_setup_timings()
107 setbits_le32(txdone, txdone_mask); in abb_setup()
110 setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK); in abb_setup()
113 setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK); in abb_setup()
120 setbits_le32(txdone, txdone_mask); in abb_setup()
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun50i_h616.c131 setbits_le32(&ccm->mbus_cfg, MBUS_RESET); in mctl_sys_init()
132 setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE); in mctl_sys_init()
280 setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4); in mctl_phy_write_leveling()
309 setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4); in mctl_phy_write_leveling()
333 setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1); in mctl_phy_read_calibration()
568 setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8); in mctl_phy_bit_delay_compensation()
746 setbits_le32(&mctl_ctl->dfimisc, 1); in mctl_phy_init()
749 setbits_le32(&mctl_ctl->dfimisc, 0x20); in mctl_phy_init()
875 setbits_le32(&mctl_com->cr, BIT(31)); in mctl_ctrl_init()
897 setbits_le32(&mctl_ctl->clken, BIT(8)); in mctl_ctrl_init()
[all …]
A Ddram_sun50i_h6.c182 setbits_le32(&ccm->dram_gate_reset, BIT(0)); in mctl_sys_init()
190 setbits_le32(&ccm->mbus_cfg, MBUS_RESET); in mctl_sys_init()
191 setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE); in mctl_sys_init()
297 setbits_le32(&mctl_com->cr, BIT(31)); in mctl_com_init()
303 setbits_le32(&mctl_com->cr, BIT(27)); in mctl_com_init()
401 setbits_le32(&mctl_phy->pgcr[0], BIT(26)); in mctl_bit_delay_set()
428 setbits_le32(&mctl_ctl->rfshctl3, BIT(0)); in mctl_channel_init()
429 setbits_le32(&mctl_ctl->dfimisc, BIT(0)); in mctl_channel_init()
430 setbits_le32(&mctl_ctl->unk_0x00c, BIT(8)); in mctl_channel_init()
525 setbits_le32(&mctl_phy->pgcr[6], BIT(0)); in mctl_channel_init()
[all …]
A Dclock_sun9i.c61 setbits_le32(&ccm->ahb_reset1_cfg, (1 << 24)); in clock_init_safe()
62 setbits_le32(&ccm->apb1_gate, (1 << 24)); in clock_init_safe()
75 setbits_le32(&ccm->apb1_gate, in clock_init_uart()
79 setbits_le32(&ccm->apb1_reset_cfg, in clock_init_uart()
184 setbits_le32(&ccm->apb1_gate, in clock_twi_onoff()
186 setbits_le32(&ccm->apb1_reset_cfg, in clock_twi_onoff()
/u-boot/drivers/usb/dwc3/
A Dsamsung_usb_phy.c27 setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL); in exynos5_usb3_phy_init()
36 setbits_le32(&phy->link_system, in exynos5_usb3_phy_init()
42 setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH); in exynos5_usb3_phy_init()
44 setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL); in exynos5_usb3_phy_init()
/u-boot/drivers/ram/sifive/
A Dfu540_ddr.c130 setbits_le32(DENALI_CTL_224 + ctl, in fu540_ddr_setup_range_protection()
134 setbits_le32(DENALI_CTL_208 + ctl, in fu540_ddr_setup_range_protection()
143 setbits_le32(DENALI_CTL_0 + ctl, 0x1); in fu540_ddr_start()
268 setbits_le32(DENALI_CTL_120 + denali_ctl, in fu540_ddr_setup()
275 setbits_le32(DENALI_CTL_170 + denali_ctl, (1 << WRLVL_EN_OFFSET) in fu540_ddr_setup()
279 setbits_le32(DENALI_CTL_181 + denali_ctl, in fu540_ddr_setup()
281 setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_EN_OFFSET); in fu540_ddr_setup()
285 setbits_le32(DENALI_CTL_182 + denali_ctl, in fu540_ddr_setup()
290 setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET); in fu540_ddr_setup()
294 setbits_le32(DENALI_CTL_136 + denali_ctl, in fu540_ddr_setup()
[all …]
/u-boot/arch/arm/mach-socfpga/
A Dfreeze_controller.c130 setbits_le32(ioctrl_reg_offset, reg_cfg_mask); in sys_mgr_frzctrl_thaw_req()
139 setbits_le32(ioctrl_reg_offset, reg_cfg_mask); in sys_mgr_frzctrl_thaw_req()
145 setbits_le32(ioctrl_reg_offset, in sys_mgr_frzctrl_thaw_req()
161 setbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
191 setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); in sys_mgr_frzctrl_thaw_req()
204 setbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
A Dreset_manager_arria10.c62 setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST, in socfpga_watchdog_disable()
99 setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_IDLEREQ_CLR, in socfpga_reset_deassert_bridges_handoff()
149 setbits_le32(socfpga_get_rstmgr_addr() + reg, in socfpga_per_reset()
179 setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST, in socfpga_per_reset_all()
183 setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST, in socfpga_per_reset_all()
233 setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST, in socfpga_bridges_reset()
/u-boot/board/hisilicon/poplar/
A Dpoplar.c129 setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ | in usb2_phy_init()
134 setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1); in usb2_phy_init()
138 setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN); in usb2_phy_init()
152 setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN | in usb2_phy_init()
175 setbits_le32(PERI_CTRL_USB3, USB2_2P_CHIPID); in set_usb_to_device()
/u-boot/drivers/mtd/
A Dstm32_flash.c27 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_LOCK); in stm32_flash_lock()
105 setbits_le32(&STM32_FLASH->cr, in flash_erase()
108 setbits_le32(&STM32_FLASH->cr, in flash_erase()
114 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER); in flash_erase()
115 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_STRT); in flash_erase()
136 setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG); in write_buff()
/u-boot/drivers/clk/owl/
A Dclk_owl.c29 setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0)); in owl_clk_init()
63 setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK); in owl_clk_init()
80 setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5); in owl_clk_enable()
88 setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3); in owl_clk_enable()
92 setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH); in owl_clk_enable()
93 setbits_le32(priv->base + CMU_ETHERNETPLL, 5); in owl_clk_enable()
/u-boot/arch/arm/cpu/arm926ejs/mxs/
A Dspl_power_init.c73 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq, in mxs_power_clock2pll()
106 setbits_le32(&rtc_regs->hw_rtc_persistent0, in mxs_power_set_auto_restart()
267 setbits_le32(&power_regs->hw_power_misc, in mxs_power_switch_dcdc_clocksource()
406 setbits_le32(&power_regs->hw_power_5vctrl, in mxs_enable_4p2_dcdc_input()
412 setbits_le32(&power_regs->hw_power_5vctrl, in mxs_enable_4p2_dcdc_input()
415 setbits_le32(&power_regs->hw_power_dcdc4p2, in mxs_enable_4p2_dcdc_input()
454 setbits_le32(&power_regs->hw_power_ctrl, in mxs_enable_4p2_dcdc_input()
524 setbits_le32(&power_regs->hw_power_5vctrl, in mxs_power_init_4p2_regulator()
745 setbits_le32(&power_regs->hw_power_5vctrl, in mxs_batt_boot()
748 setbits_le32(&power_regs->hw_power_5vctrl, in mxs_batt_boot()
[all …]

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