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/u-boot/arch/arm/dts/
A Dk3-am654.dtsi43 i-cache-sets = <256>;
46 d-cache-sets = <128>;
57 i-cache-sets = <256>;
60 d-cache-sets = <128>;
71 i-cache-sets = <256>;
74 d-cache-sets = <128>;
85 i-cache-sets = <256>;
88 d-cache-sets = <128>;
98 cache-sets = <512>;
107 cache-sets = <512>;
A Dk3-j7200.dtsi60 i-cache-sets = <256>;
63 d-cache-sets = <128>;
74 i-cache-sets = <256>;
77 d-cache-sets = <128>;
87 cache-sets = <2048>;
A Dk3-j721e.dtsi61 i-cache-sets = <256>;
64 d-cache-sets = <128>;
75 i-cache-sets = <256>;
78 d-cache-sets = <128>;
88 cache-sets = <2048>;
/u-boot/arch/riscv/dts/
A Dfu540-c000.dtsi29 i-cache-sets = <128>;
43 d-cache-sets = <64>;
45 d-tlb-sets = <1>;
49 i-cache-sets = <64>;
51 i-tlb-sets = <1>;
69 d-tlb-sets = <1>;
75 i-tlb-sets = <1>;
93 d-tlb-sets = <1>;
99 i-tlb-sets = <1>;
117 d-tlb-sets = <1>;
[all …]
A Dmicrochip-mpfs-icicle-kit.dts34 i-cache-sets = <128>;
55 d-cache-sets = <64>;
57 d-tlb-sets = <1>;
61 i-cache-sets = <64>;
63 i-tlb-sets = <1>;
88 d-tlb-sets = <1>;
94 i-tlb-sets = <1>;
119 d-tlb-sets = <1>;
125 i-tlb-sets = <1>;
150 d-tlb-sets = <1>;
[all …]
/u-boot/arch/arm/cpu/armv7m/
A Dcache.c64 u32 sets; member
72 cache->sets = (cache_size_id & MASK_NUM_SETS) >> NUM_SETS_SHIFT; in get_cache_ways_sets()
189 debug("cache: ways= %d, sets= %d\n", cache.ways + 1, cache.sets + 1); in action_dcache_all()
190 for (i = cache.sets; i >= 0; i--) { in action_dcache_all()
/u-boot/doc/board/google/
A Dchromebook_link.rst11 * mrc.bin - Memory Reference Code, which sets up SDRAM
12 * video ROM - sets up the display
A Dchromebook_samus.rst11 * mrc.bin - Memory Reference Code, which sets up SDRAM
13 * vga.bin - video ROM, which sets up the display
A Dchromebook_coral.rst26 sets up some SDRAM at ffff8000 and loads the TPL image to that address. The
34 TPL (running from start.S) first sets up CAR (Cache-as-RAM) which provides
36 (fef00000) and is 768KB in size. It then sets up the stack in the botttom 64KB
80 SPL sets up a bloblist and passes the SPL hand-off information to U-Boot proper.
99 arch_cpu_init_dm() sets up the pin muxing for the chip using a very large table
/u-boot/doc/usage/
A Dfalse.rst14 The false command sets the return value $? to 1 (false).
A Dtrue.rst14 The true command sets the return value $? to 0 (true).
A Dbase.rst16 The *base* command sets or displays the address offset used by the memory
/u-boot/doc/device-tree-bindings/gpio/
A Dintel,x86-broadwell-pinctrl.txt14 - output-value - sets the default output value of the GPIO, 0 (low, default)
16 - direction - sets the direction of the gpio, either PIN_INPUT (default)
19 - trigger - sets the trigger type, either TRIGGER_EDGE (default) or
22 - owner 0 sets the owner of the pin, either OWNER_ACPI (default) or
24 - route - sets whether the pin is routed, either PIRQ_APIC_MASK or
/u-boot/board/advantech/dms-ba16/
A Dclocks.cfg23 * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
/u-boot/board/boundary/nitrogen6x/
A Dclocks.cfg38 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
/u-boot/doc/
A DREADME.mpc74xx12 sets up the L2 cache, so it's not enabled. (IMHO, it shouldn't be
A DREADME.mpc85xx-spin-table9 Core 0 sets up the reset page on the top 4K of memory (or 4GB if total memory
A DREADME.nand-boot-ppc44021 has to fit into 4kByte. It sets up the CPU and configures the SDRAM
/u-boot/drivers/firmware/
A Dti_sci.c3025 for (set = 0; set < res->sets; set++) { in ti_sci_get_free_resource()
3045 for (set = 0; set < res->sets; set++) { in ti_sci_release_resource()
3074 int sets, i, ret; in devm_ti_sci_get_of_resource() local
3081 sets = dev_read_size(dev, of_prop); in devm_ti_sci_get_of_resource()
3082 if (sets < 0) { in devm_ti_sci_get_of_resource()
3084 return ERR_PTR(sets); in devm_ti_sci_get_of_resource()
3086 temp = malloc(sets); in devm_ti_sci_get_of_resource()
3087 sets /= sizeof(u32); in devm_ti_sci_get_of_resource()
3088 res->sets = sets; in devm_ti_sci_get_of_resource()
3095 ret = dev_read_u32_array(dev, of_prop, temp, res->sets); in devm_ti_sci_get_of_resource()
[all …]
/u-boot/doc/device-tree-bindings/exynos/
A Dtmu.txt23 - It sets the gain of amplifier to the positive-tc generator block.
/u-boot/doc/device-tree-bindings/remoteproc/
A Dk3-rproc.txt13 - power-domains: Should contain two sets of entries:
/u-boot/doc/android/
A Dab.rst10 allows one to use two sets (or more) of partitions referred to as slots
/u-boot/doc/device-tree-bindings/phy/
A Dphy-stm32-usbphyc.txt5 selects either OTG or HOST controller for the second PHY port. It also sets
/u-boot/doc/device-tree-bindings/arm/
A Dl2c2x0.txt53 - cache-sets : specifies the number of associativity sets of the cache
/u-boot/doc/driver-model/
A Dsoc-framework.rst48 different sets of SoC data using soc_device_match.

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