| /u-boot/board/imgtec/malta/ |
| A D | lowlevel_init.S | 32 lw t0, 0(t0)
33 srl t0, t0, MALTA_REVISION_CORID_SHF
34 andi t0, t0, (MALTA_REVISION_CORID_MSK >> \
39 beq t0, t1, _gt64120
43 beq t0, t1, _msc01
67 sw t0, GT_ISD_OFS(t1)
74 sw t0, GT_PCI0IOLD_OFS(t1)
76 sw t0, GT_PCI0IOHD_OFS(t1)
80 sw t0, GT_PCI0M0LD_OFS(t1)
82 sw t0, GT_PCI0M0HD_OFS(t1)
[all …]
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| /u-boot/arch/mips/mach-jz47xx/ |
| A D | start.S | 29 ori t0, 2
46 la t0, CPM_BASE
47 lw t1, 0x24(t0)
49 sw t1, 0x24(t0)
66 li t0, KSEG0
70 bne t0, t1, 1b
71 addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
73 li t0, KSEG0
77 bne t0, t1, 2b
78 addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
[all …]
|
| /u-boot/arch/mips/mach-ath79/qca956x/ |
| A D | qca956x-ddr-tap.S | 52 lw t1, 0x0(t0)
125 lw t1, 0x4(t0)
127 sw t1, 0x4(t0)
130 lw t1, 0x0(t0)
136 lw t1, 0x0(t0)
138 sw t1, 0x4(t0)
145 lw t1, 0x0(t0)
147 sw t1, 0x0(t0)
148 sw t1, 0x4(t0)
153 lw t1, 0x0(t0)
[all …]
|
| /u-boot/arch/mips/cpu/ |
| A D | cm_init.S | 16 mfc0 t0, CP0_CONFIG, 1
17 bgez t0, 2f
18 mfc0 t0, CP0_CONFIG, 2
19 bgez t0, 2f
22 mfc0 t0, CP0_CONFIG, 3
23 and t0, t0, MIPS_CONF3_CMGCR
24 beqz t0, 2f
28 PTR_SLL t0, t0, 4
32 beq t0, t1, 2f
36 PTR_ADDU t0, t0, t2
[all …]
|
| A D | start.S | 33 bgez t0, wr_done
46 li t0, -16
63 move t0, k0
65 PTR_S zero, 0(t0)
67 blt t0, t1, 1b
134 and t0, t0, MIPS_CONF5_VP
135 beqz t0, 1f
144 and t0, t0, (1 << 31)
147 and t0, t0, MIPS_EBASE_CPUNUM
151 2: beqz t0, 4f
[all …]
|
| /u-boot/arch/riscv/cpu/ |
| A D | start.S | 82 li t0, MIE_MSIE
93 li t0, -16
115 sub sp, a0, t0
205 addi t0, t0, REGBYTES
286 addi t0, t0, REGBYTES
330 mul t0, t0, t5
346 add t0, t0, t6
351 add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
358 addi t0, t0, REGBYTES
436 andi t0, t0, MIE_MSIE
[all …]
|
| /u-boot/arch/mips/lib/ |
| A D | cache_init.S | 90 and t0, t0, t1
92 or t0, t0, t1
94 jalr t0
225 or t0, t0, MIPS_CONF2_L2B
287 PTR_ADDU t0, t0, R_L2_LINE
288 bne t0, t1, 1b
379 xor t0, t0, MIPS_CONF2_L2B
387 bgez t0, 2f
389 bgez t0, 2f
393 and t0, t0, MIPS_CONF3_CMGCR
[all …]
|
| /u-boot/arch/mips/mach-mtmips/mt7628/ |
| A D | lowlevel_init.S | 41 subu t0, t0, 1
68 mfc0 t0, CP0_ECC
69 ins t0, zero, 30, 2
70 mtc0 t0, CP0_ECC
96 mfc0 t0, CP0_CONFIG
97 and t0, t0, MIPS_CONF_IMPL
98 or t0, t0, CONF_CM_CACHABLE_NONCOHERENT
99 mtc0 t0, CP0_CONFIG
109 and t0, a0, a2
154 and t0, t0, MIPS_CONF_IMPL
[all …]
|
| /u-boot/arch/mips/mach-ath79/ar933x/ |
| A D | lowlevel_init.S | 81 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
110 li t0, CKSEG1ADDR(AR933X_RTC_BASE)
112 sw t1, AR933X_RTC_REG_FORCE_WAKE(t0)
118 sw t1, AR933X_RTC_REG_RESET(t0)
123 sw t1, AR933X_RTC_REG_RESET(t0)
129 lw t1, AR933X_RTC_REG_STATUS(t0)
135 li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
157 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
159 sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
271 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
[all …]
|
| /u-boot/arch/mips/mach-ath79/qca953x/ |
| A D | lowlevel_init.S | 101 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
114 li t0, CKSEG1ADDR(QCA953X_RTC_BASE)
127 li t0, CKSEG1ADDR(QCA953X_SRIF_BASE)
129 sw t1, QCA953X_SRIF_BB_DPLL2_REG(t0)
134 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
135 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
137 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
149 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
164 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
167 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
[all …]
|
| /u-boot/arch/mips/mach-mtmips/mt7620/ |
| A D | lowlevel_init.S | 29 li t0, -16
30 and sp, sp, t0 # force 16 byte alignment
36 move t0, k0
38 PTR_S zero, 0(t0)
39 PTR_ADDIU t0, PTRSIZE
40 blt t0, t1, 1b
|
| /u-boot/arch/mips/mach-octeon/ |
| A D | lowlevel_init.S | 60 daddu t0, t1, t3 /* t0 now has actual address of _start */
70 ld a0, 0(t0)
71 ld a1, 8(t0)
72 ld a2, 16(t0)
73 ld a3, 24(t0)
78 addiu t0, 32
|
| /u-boot/board/coreboot/coreboot/ |
| A D | coreboot.c | 33 const struct smbios_type0 *t0 = (struct smbios_type0 *)bios; in show_board_info() local
36 if (!t0 || !t1) in show_board_info()
39 const char *bios_ver = smbios_string(bios, t0->bios_ver); in show_board_info()
|
| /u-boot/arch/mips/mach-mscc/ |
| A D | lowlevel_init.S | 23 li t0, 0x0fffffff
25 and s0, ra, t0
|
| /u-boot/board/imgtec/boston/ |
| A D | lowlevel_init.S | 28 PTR_LI t0, BOSTON_PLAT_DDR3STAT
29 1: lw t1, 0(t0)
|
| /u-boot/arch/mips/include/asm/ |
| A D | regdef.h | 27 #define t0 $8 /* caller saved */ macro
78 #define t0 $12 /* caller saved */ macro
|
| /u-boot/arch/nds32/cpu/n1213/ |
| A D | start.S | 318 mfsr $t0, CR_ICAC_MEM
321 andi $p0, $t0, ICAC_MEM_KBF_ISZ
334 andi $p1, $t0, ICAC_MEM_KBF_ISET ! get the ISET field
336 andi $p1, $t0, ICAC_MEM_KBF_IWAY ! get bitfield of Iway
353 mfsr $t0, CR_DCAC_MEM
356 andi $p0, $t0, DCAC_MEM_KBF_DSZ
369 andi $p1, $t0, DCAC_MEM_KBF_DSET ! get the DSET field
371 andi $p1, $t0, DCAC_MEM_KBF_DWAY ! get bitfield of D way
|
| /u-boot/tools/buildman/ |
| A D | kconfiglib.py | 2915 t0 = self._tokens[0]
2917 if t0 is _T_CONFIG or t0 is _T_MENUCONFIG:
2955 elif t0 is None:
2992 elif t0 is end_token:
3002 elif t0 is _T_IF:
3013 elif t0 is _T_MENU:
3142 t0 = self._tokens[0]
3157 elif t0 is _T_HELP:
3167 elif t0 is None:
3183 elif t0 is _T_RANGE:
[all …]
|
| /u-boot/arch/riscv/include/asm/ |
| A D | ptrace.h | 18 unsigned long t0; member
|
| /u-boot/arch/riscv/lib/ |
| A D | interrupts.c | 34 regs->t0, regs->t1, regs->t2); in show_regs()
|
| /u-boot/drivers/clk/mvebu/ |
| A D | armada-37xx-periph.c | 365 static ulong find_best_div(const struct clk_div_table *t0, in find_best_div() argument
372 for (i = t0; i && i->div; ++i) { in find_best_div()
|
| /u-boot/arch/arm/dts/ |
| A D | k3-j721e-main.dtsi | 428 compatible = "ti,sierra-phy-t0";
485 compatible = "ti,sierra-phy-t0";
542 compatible = "ti,sierra-phy-t0";
599 compatible = "ti,sierra-phy-t0";
|
| /u-boot/drivers/video/ |
| A D | stb_truetype.h | 269 glTexCoord2f(q.s1,q.t0); glVertex2f(q.x1,q.y1);
270 glTexCoord2f(q.s0,q.t0); glVertex2f(q.x0,q.y1);
480 float x0,y0,s0,t0; // top-left member
2574 q->t0 = b->y0 * iph; in stbtt_GetBakedQuad()
3030 q->t0 = b->y0 * iph; in stbtt_GetPackedQuad()
|
| /u-boot/drivers/mtd/nand/raw/ |
| A D | octeontx_nand.c | 350 t0, /* fixed at 4<<mult cycles */ enumerator
|
| /u-boot/ |
| A D | README | 4353 x5: link register (t0)
|