| /u-boot/arch/mips/mach-mtmips/mt7628/ |
| A D | lowlevel_init.S | 38 lw t3, 0(t1)
39 andi t3, t3, 1
40 bnez t3, _rom_normal
45 lw t3, 0(t2)
52 lw t3, 0(t2)
58 sw t3, 0(t2)
61 lw t3, 0(t2)
62 ori t3, t3, (CPU_FDIV_M | CPU_FFRAC_M)
63 xori t3, t3, (CPU_FDIV_M | CPU_FFRAC_M)
64 ori t3, t3, ((1 << CPU_FDIV_S) | (1 << CPU_FFRAC_S))
[all …]
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| /u-boot/arch/mips/mach-ath79/qca956x/ |
| A D | qca956x-ddr-tap.S | 54 or t3, t1, t2
57 sw t3, 0x1c(t0) /* TAP_CONTROL_0_ADDRESS */
58 sw t3, 0x20(t0) /* TAP_CONTROL_1_ADDRESS */
117 li t3, 0x000001fe
118 and t3, t3, t1
119 srl t3, t3, 0x1 /* No. of runs in the config register. */
120 bne t3, t2, _iterate_tap
170 li t3, 0x8 /* Default Tap to be used */
178 add t3, t1, t2
179 srl t3, t3, 0x1
[all …]
|
| /u-boot/arch/riscv/cpu/ |
| A D | start.S | 280 la t3, __bss_start
281 sub t3, t3, t0 /* t3 <- __bss_start_ofs */
282 add t2, t0, t3 /* t2 <- source end address */
310 LREG t3, -(REGBYTES*3)(t1)
313 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
314 SREG t5, 0(t3)
325 li t3, RELOC_TYPE
326 bne t5, t3, 10f /* skip non-addned entries */
328 LREG t3, -(REGBYTES*3)(t1)
336 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
[all …]
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| /u-boot/arch/mips/mach-ath79/ar933x/ |
| A D | lowlevel_init.S | 79 li t3, 0x03
91 addi t3, t3, -1
92 bnez t3, 1b
222 li t3, 100
227 bgt t4, t3, 0b
230 li t3, 5
266 addi t3, t3, -1
267 bnez t3, 3b
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| /u-boot/arch/mips/include/asm/ |
| A D | regdef.h | 30 #define t3 $11 macro
81 #define t3 $15 macro
|
| /u-boot/arch/mips/mach-octeon/ |
| A D | lowlevel_init.S | 57 dsubu t3, ra, a7 /* t3 now has reloc offset */
60 daddu t0, t1, t3 /* t0 now has actual address of _start */
91 dsubu s0, s0, t3 /* Fixup return address with reloc offset */
|
| /u-boot/board/imgtec/malta/ |
| A D | lowlevel_init.S | 157 li t3, MALTA_MSC01_PCIMEM_MAP
160 sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0)
165 li t3, MALTA_MSC01_PCIIO_MAP
168 sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
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| /u-boot/arch/powerpc/lib/ |
| A D | _ashrdi3.S | 37 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
|
| /u-boot/scripts/coccinelle/null/ |
| A D | badzero.cocci | 216 @ t3 depends on !patch disable is_zero,isnt_zero @
232 p << t3.p;
238 p << t3.p;
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| /u-boot/arch/riscv/include/asm/ |
| A D | ptrace.h | 41 unsigned long t3; member
|
| /u-boot/arch/mips/lib/ |
| A D | cache_init.S | 406 li t3, GCR_Cx_COHERENCE_EN
408 li t3, GCR_Cx_COHERENCE_DOM_EN
409 1: sw t3, GCR_Cx_COHERENCE(t0)
|
| /u-boot/arch/nds32/cpu/n1213/ |
| A D | start.S | 339 add $t3, $t2, $t1 ! SHIFT
340 sll $p1, $p1, $t3 ! GET the total cache size
374 add $t3, $t2, $t1 ! SHIFT
375 sll $p1, $p1, $t3 ! GET the total cache size
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| /u-boot/arch/riscv/lib/ |
| A D | interrupts.c | 48 regs->s10, regs->s11, regs->t3); in show_regs()
|
| /u-boot/drivers/mtd/nand/raw/ |
| A D | octeontx_nand.c | 351 t1, t2, t3, t4, t5, t6, t7, /* settable per ONFI-timing mode */ enumerator
856 cmd.u.ale_cmd.alen1 = t3; in ndf_queue_cmd_ale()
870 cmd.u.wr_cmd.wlen1 = t3; in ndf_queue_cmd_write()
1042 cmd.u.rd_cmd.rlen2 = t3; in ndf_read()
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| /u-boot/ |
| A D | README | 4357 x28-31: temporaries (t3-6)
|