| /u-boot/arch/arm/mach-sunxi/dram_timings/ |
| A D | h6_ddr3_1333.c | 78 u8 tcl = 6; /* JEDEC: CL / 2 => 6 */ in mctl_set_timing_params() local
91 if (tcl + 1 >= trtp + trp) in mctl_set_timing_params()
92 trtp = tcl + 2 - trp; in mctl_set_timing_params()
102 writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, in mctl_set_timing_params()
134 writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000, in mctl_set_timing_params()
|
| A D | h6_lpddr3.c | 64 u8 tcl = 5; /* CL 10 */ in mctl_set_timing_params() local
80 u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1; in mctl_set_timing_params()
90 writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, in mctl_set_timing_params()
122 writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000, in mctl_set_timing_params()
|
| A D | h616_ddr3_1333.c | 48 u8 tcl = 7; /* JEDEC: CL / 2 => 6 */ in mctl_set_timing_params() local
60 writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd, in mctl_set_timing_params()
88 writel((tcl - 2) | 0x2000000 | (t_rdata_en << 16) | 0x808000, in mctl_set_timing_params()
|
| A D | ddr3_1333.c | 33 u8 tcl = 6; /* CL 12 */ in mctl_set_timing_params() local
45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in mctl_set_timing_params()
62 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | in mctl_set_timing_params()
|
| A D | lpddr3_stock.c | 33 u8 tcl = 6; /* CL 12 */ in mctl_set_timing_params() local
45 u8 trd2wr = tcl + 4 + 5 - tcwl + 1; in mctl_set_timing_params()
58 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | in mctl_set_timing_params()
|
| A D | ddr2_v3s.c | 33 u8 tcl = 3; /* CL 6 */ in mctl_set_timing_params() local
45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in mctl_set_timing_params()
59 writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | in mctl_set_timing_params()
|
| /u-boot/board/tcl/sl50/ |
| A D | Kconfig | 7 default "tcl"
|
| A D | MAINTAINERS | 4 F: board/tcl/sl50/
|
| /u-boot/drivers/ram/rockchip/ |
| A D | dmc-rk3368.c | 160 u32 tcl, u32 tal, u32 tcwl) in ddrphy_config() argument
168 clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal); in ddrphy_config()
243 DDR3_MR0_CL(params->pctl_timing.tcl) | in memory_init()
477 pctl_timing->tcl = 6; in pctl_calc_timings()
480 pctl_timing->tcl = 8; in pctl_calc_timings()
483 pctl_timing->tcl = 10; in pctl_calc_timings()
486 pctl_timing->tcl = 11; in pctl_calc_timings()
498 pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl; in pctl_calc_timings()
564 writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen); in pctl_cfg()
835 params->pctl_timing.tcl, in setup_sdram()
|
| A D | sdram_rk3288.c | 255 writel(sdram_params->pctl_timing.tcl - 1, in pctl_cfg()
272 writel(sdram_params->pctl_timing.tcl - 3, in pctl_cfg()
275 writel(sdram_params->pctl_timing.tcl - 2, in pctl_cfg()
|
| A D | sdram_rk322x.c | 431 writel((readl(&pctl->tcl) - 1) / 2 - 1, &pctl->dfitrddataen); in pctl_cfg()
445 writel(readl(&pctl->tcl) / 2 - 1, &pctl->dfitrddataen); in pctl_cfg()
|
| /u-boot/doc/ |
| A D | README.malta | 12 source /path/to/u-boot/board/imgtec/malta/flash-malta-boot.tcl
|
| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun8i_a83t.c | 118 u8 tcl = 6; /* CL 12 */ in auto_set_timing_para() local
130 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
169 trd2wr = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
176 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
|
| A D | dram_sun8i_a33.c | 118 u8 tcl = 6; /* CL 12 */ in auto_set_timing_para() local
130 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
144 reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0); in auto_set_timing_para()
|
| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | sdram_rk3288.h | 48 u32 tcl; member
|
| A D | sdram_rk3036.h | 49 u32 tcl; member
246 u32 tcl; member
|
| A D | sdram_rk322x.h | 82 u32 tcl; member
208 u32 tcl; member
|
| A D | ddr_rk3368.h | 59 u32 tcl; member
|
| A D | ddr_rk3288.h | 50 u32 tcl; member
|
| /u-boot/arch/arm/mach-imx/mx6/ |
| A D | ddr.c | 1047 u8 twl, txp, tfaw, tcl; in mx6_lpddr2_cfg() local
1114 tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3; in mx6_lpddr2_cfg()
1135 debug("tcl=%d\n", tcl); in mx6_lpddr2_cfg()
1189 (tfaw << 4) | tcl; in mx6_lpddr2_cfg()
1279 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; in mx6_ddr3_cfg() local
1386 tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3; in mx6_ddr3_cfg()
1410 debug("tcl=%d\n", tcl); in mx6_ddr3_cfg()
1483 (txpdll << 9) | (tfaw << 4) | tcl; in mx6_ddr3_cfg()
1538 val = ((tcl - 1) << 4) | /* CAS */ in mx6_ddr3_cfg()
1593 ((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT) | in mx6_ddr3_cfg()
|
| /u-boot/doc/device-tree-bindings/misc/ |
| A D | intel,baytrail-fsp.txt | 81 - fsp,dimm-tcl
144 fsp,dimm-tcl = <0xb>;
|
| /u-boot/arch/x86/cpu/quark/ |
| A D | smc.c | 65 uint8_t tcl, wl; in prog_ddr_timing_control() local
83 tcl = mrc_params->params.cl; /* CAS latency in clocks */ in prog_ddr_timing_control()
84 trp = tcl; /* Per CAT MRC */ in prog_ddr_timing_control()
85 trcd = tcl; /* Per CAT MRC */ in prog_ddr_timing_control()
101 tmp1 = tcl - 5; in prog_ddr_timing_control()
102 dtr0 |= ((tcl - 5) << 12); in prog_ddr_timing_control()
141 dtr3 |= ((tcl - 5 + 1) << 8); in prog_ddr_timing_control()
144 dtr3 |= ((tcl - 5 + 1) << 8); in prog_ddr_timing_control()
|
| /u-boot/board/freescale/mx6qarm2/ |
| A D | imximage_mx6dl.cfg | 284 /* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
296 /* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
|
| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | dram_sun6i.h | 82 u32 tcl; /* 0xe8 */ member
|
| /u-boot/doc/device-tree-bindings/clock/ |
| A D | rockchip,rk3288-dmc.txt | 64 tcl
|