| /u-boot/arch/arm/mach-lpc32xx/ |
| A D | timer.c | 29 writel(TIMER_TCR_COUNTER_RESET, &timer->tcr); in lpc32xx_timer_reset()
30 writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr); in lpc32xx_timer_reset()
47 writel(TIMER_TCR_COUNTER_ENABLE, &timer->tcr); in lpc32xx_timer_count()
49 writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr); in lpc32xx_timer_count()
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| /u-boot/arch/arm/include/asm/armv8/ |
| A D | mmu.h | 107 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) in set_ttbr_tcr_mair() argument
112 asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory"); in set_ttbr_tcr_mair()
116 asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory"); in set_ttbr_tcr_mair()
120 asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory"); in set_ttbr_tcr_mair()
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| /u-boot/arch/arm/mach-davinci/ |
| A D | timer.c | 44 writel(0x0, &timer->tcr); in timer_init()
49 writel(2 << 22, &timer->tcr); in timer_init()
111 writel(0x0, &wdttimer->tcr); in davinci_hw_watchdog_enable()
117 writel(2 << 22, &wdttimer->tcr); in davinci_hw_watchdog_enable()
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| A D | reset.c | 25 writel(readl(&wdttimer->tcr) | 0x40, &wdttimer->tcr); in reset_cpu()
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| /u-boot/arch/m68k/include/asm/ |
| A D | timer.h | 25 u16 tcr; /* 0x08 Capture register */ member
37 u32 tcr; /* 0x08 Capture register */
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| A D | fsl_mcdmafec.h | 30 u32 tcr; /* 0x0C4 */ member
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| A D | fec.h | 131 u32 tcr; /* 0x144 */ member
160 u32 tcr;
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| /u-boot/arch/arm/mach-at91/include/mach/ |
| A D | at91_pdc.h | 13 u32 tcr; /* 0x10C Transmit Counter Register */ member
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| A D | at91_emac.h | 16 u32 tcr; member
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| A D | at91_matrix.h | 52 u32 tcr; member
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| /u-boot/drivers/net/ |
| A D | fsl_mcdmafec.c | 88 fecp->tcr |= FEC_TCR_GTS; in fec_halt()
133 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); in dbg_fec_regs()
171 fecp->tcr = FEC_TCR_FDEN; in set_fec_duplex_speed()
176 fecp->tcr &= ~FEC_TCR_FDEN; in set_fec_duplex_speed()
437 fecp->tcr |= FEC_TCR_GTS; in mcdmafec_recv()
442 if (fecp->tcr & FEC_TCR_GTS) { in mcdmafec_recv()
445 fecp->tcr &= ~FEC_TCR_GTS; in mcdmafec_recv()
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| A D | mcffec.c | 99 fecp->tcr = FEC_TCR_FDEN; in set_fec_duplex_speed()
104 fecp->tcr &= ~FEC_TCR_FDEN; in set_fec_duplex_speed()
142 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); in dbg_fec_regs()
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| A D | at91_emac.c | 403 writel(AT91_EMAC_TCR_LEN(length), &emac->tcr); in at91emac_send()
404 while (AT91_EMAC_TCR_LEN(readl(&emac->tcr))) in at91emac_send()
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| /u-boot/arch/arm/cpu/armv8/ |
| A D | cache_v8.c | 46 u64 tcr; in get_tcr() local
75 tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE; in get_tcr()
77 tcr = TCR_EL2_RSVD | (ips << 16); in get_tcr()
79 tcr = TCR_EL3_RSVD | (ips << 16); in get_tcr()
83 tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA; in get_tcr()
84 tcr |= TCR_T0SZ(va_bits); in get_tcr()
91 return tcr; in get_tcr()
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| /u-boot/arch/arm/mach-davinci/include/mach/ |
| A D | timer_defs.h | 18 u_int32_t tcr; member
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| /u-boot/arch/arm/include/asm/arch-lpc32xx/ |
| A D | timer.h | 14 u32 tcr; /* Timer Control Register */ member
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| /u-boot/arch/m68k/include/asm/coldfire/ |
| A D | dspi.h | 16 u32 tcr; /* 0x08 */ member
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| A D | ssi.h | 20 u32 tcr; member
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| /u-boot/include/ |
| A D | fsl_dspi.h | 18 u32 tcr; /* 0x08 */ member
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| /u-boot/drivers/usb/eth/ |
| A D | r8152.c | 58 unsigned short tcr; member
1150 u16 tcr; in r8152b_get_version() local
1154 tcr = (u16)(ocp_data & VERSION_MASK); in r8152b_get_version()
1157 if (tcr == r8152_versions[i].tcr) { in r8152b_get_version()
1166 debug("r8152 Unknown tcr version 0x%04x\n", tcr); in r8152b_get_version()
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| /u-boot/arch/powerpc/include/asm/ |
| A D | immap_86xx.h | 593 uint tcr; /* 0x41300 - Timer Control Register */ member
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| A D | immap_85xx.h | 694 u32 tcr; /* Timer Control */ member
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| /u-boot/drivers/mmc/ |
| A D | fsl_esdhc_imx.c | 108 uint tcr; /* Tuning control register */ member
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| /u-boot/ |
| A D | README | 4122 …tgcr @ 0xfff00980, tmr @ 0xfff00990, trr @ 0xfff00994, tcr @ 0xfff00998, tcn @ 0xfff0099c, ter @ 0…
4129 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0xef6, ter=0x0
4132 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x2ad4, ter=0x0
4135 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x1efc, ter=0x0
4138 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x169d, ter=0x0
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