| /u-boot/arch/arm/mach-sunxi/dram_timings/ |
| A D | h6_lpddr3.c | 29 u8 tfaw = max(ns_to_t(50), 4); in mctl_set_timing_params() local
87 writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, in mctl_set_timing_params()
113 writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]); in mctl_set_timing_params()
|
| A D | h6_ddr3_1333.c | 50 u8 tfaw = ns_to_t(50); /* JEDEC: 30 ns w/ 1K pages */ in mctl_set_timing_params() local
99 writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, in mctl_set_timing_params()
125 writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]); in mctl_set_timing_params()
|
| A D | h616_ddr3_1333.c | 24 u8 tfaw = ns_to_t(50); /* JEDEC: 30 ns w/ 1K pages */ in mctl_set_timing_params() local
57 writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, in mctl_set_timing_params()
|
| A D | ddr2_v3s.c | 11 u8 tfaw = ns_to_t(50); in mctl_set_timing_params() local
54 writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | in mctl_set_timing_params()
|
| A D | ddr3_1333.c | 11 u8 tfaw = ns_to_t(50); in mctl_set_timing_params() local
57 writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | in mctl_set_timing_params()
|
| A D | lpddr3_stock.c | 11 u8 tfaw = max(ns_to_t(50), 4); in mctl_set_timing_params() local
53 writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | in mctl_set_timing_params()
|
| /u-boot/arch/arm/mach-imx/mx6/ |
| A D | ddr.c | 1047 u8 twl, txp, tfaw, tcl; in mx6_lpddr2_cfg() local
1092 tfaw = DIV_ROUND_UP(60000, clkper) - 1; in mx6_lpddr2_cfg()
1094 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_lpddr2_cfg()
1134 debug("tfaw=%d\n", tfaw); in mx6_lpddr2_cfg()
1189 (tfaw << 4) | tcl; in mx6_lpddr2_cfg()
1354 tfaw = DIV_ROUND_UP(40000, clkper) - 1; in mx6_ddr3_cfg()
1357 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_ddr3_cfg()
1365 tfaw = DIV_ROUND_UP(37500, clkper) - 1; in mx6_ddr3_cfg()
1368 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_ddr3_cfg()
1409 debug("tfaw=%d\n", tfaw); in mx6_ddr3_cfg()
[all …]
|
| /u-boot/arch/arm/include/asm/arch-tegra20/ |
| A D | emc.h | 51 u32 tfaw; /* 0x98: EMC_TFAW */ member
|
| /u-boot/arch/arm/include/asm/arch-vf610/ |
| A D | ddrmc-vf610.h | 25 u8 tfaw; member
|
| /u-boot/board/phytec/pcm052/ |
| A D | pcm052.c | 105 .tfaw = 18, in dram_init()
160 .tfaw = 16, in dram_init()
|
| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun8i_a83t.c | 95 u8 tfaw = ns_to_t(50); in auto_set_timing_para() local
147 tfaw = max(ns_to_t(50), 4); in auto_set_timing_para()
172 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); in auto_set_timing_para()
|
| A D | dram_sun8i_a33.c | 95 u8 tfaw = ns_to_t(50); in auto_set_timing_para() local
140 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); in auto_set_timing_para()
|
| /u-boot/doc/device-tree-bindings/misc/ |
| A D | intel,baytrail-fsp.txt | 87 - fsp,dimm-tfaw
150 fsp,dimm-tfaw = <0x14>;
|
| /u-boot/arch/arm/mach-imx/ |
| A D | ddrmc-vf610.c | 132 writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) | in ddrmc_ctrl_init_ddr3()
|
| /u-boot/board/freescale/vf610twr/ |
| A D | vf610twr.c | 99 .tfaw = 20, in dram_init()
|
| /u-boot/board/toradex/colibri_vf/ |
| A D | colibri_vf.c | 100 .tfaw = 20, in dram_init()
|
| /u-boot/arch/x86/dts/ |
| A D | conga-qeval20-qa3-e3845.dts | 299 fsp,dimm-tfaw = <22>;
|
| A D | dfi-bt700.dtsi | 317 fsp,dimm-tfaw = <22>;
|
| A D | minnowmax.dts | 316 fsp,dimm-tfaw = <0x14>;
|
| /u-boot/arch/mips/mach-octeon/include/mach/cvmx/ |
| A D | cvmx-lmcx-defs.h | 1079 uint64_t tfaw:5; member
1099 uint64_t tfaw:5; member
4141 uint64_t tfaw:5; member
4156 uint64_t tfaw:5; member
4173 uint64_t tfaw:5; member
4192 uint64_t tfaw:5; member
|
| /u-boot/arch/x86/cpu/quark/ |
| A D | smc.c | 66 uint8_t trp, trcd, tras, twr, twtr, trrd, trtp, tfaw; in prog_ddr_timing_control() local
94 tfaw = MCEIL(mrc_params->params.faw, tck); in prog_ddr_timing_control()
122 dtr1 |= ((((tfaw + 1) >> 1) - 5) << 16);/* 4 bit DRAM Clock */ in prog_ddr_timing_control()
|
| /u-boot/drivers/ram/octeon/ |
| A D | octeon3_lmc.c | 2671 static int tfaw __section(".data");
3043 tp1.cn78xx.tfaw = divide_roundup(tfaw, 4 * tclk_psecs); in lmc_timing_params1()
9271 tfaw = ddr4_tfawmin; in init_octeon3_ddr3_interface()
9409 tfaw = spd_tfaw * mtb_psec; in init_octeon3_ddr3_interface()
9436 tfaw); in init_octeon3_ddr3_interface()
|