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Searched refs:txsr (Results 1 – 18 of 18) sorted by relevance

/u-boot/board/work-microwave/work_92105/
A Dwork_92105_spl.c29 .txsr = 12500000,
49 .txsr = 8333333,
/u-boot/board/timll/devkit3250/
A Ddevkit3250_spl.c36 .txsr = 12500000,
/u-boot/arch/arm/mach-sunxi/dram_timings/
A Dh616_ddr3_1333.c34 u16 txsr = 4; /* ? */ in mctl_set_timing_params() local
76 writel(txsr, &mctl_ctl->dramtmg[14]); in mctl_set_timing_params()
A Dh6_lpddr3.c43 u16 txsr = ns_to_t(220); in mctl_set_timing_params() local
101 writel(txsr, &mctl_ctl->dramtmg[14]); in mctl_set_timing_params()
A Dh6_ddr3_1333.c64 u16 txsr = 4; /* ? */ in mctl_set_timing_params() local
113 writel(txsr, &mctl_ctl->dramtmg[14]); in mctl_set_timing_params()
/u-boot/arch/arm/include/asm/arch-tegra20/
A Demc.h49 u32 txsr; /* 0x90: EMC_TXSR */ member
/u-boot/arch/arm/include/asm/arch-vf610/
A Dddrmc-vf610.h47 u16 txsr; member
/u-boot/drivers/ram/
A Dstm32_sdram.c128 u8 txsr; member
208 | timing->txsr << FMC_SDTR_TXSR_SHIFT in stm32_sdram_init()
218 | timing->txsr << FMC_SDTR_TXSR_SHIFT in stm32_sdram_init()
/u-boot/arch/arm/mach-lpc32xx/
A Ddram.c48 writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr); in ddr_init()
/u-boot/arch/arm/include/asm/arch-lpc32xx/
A Demc.h90 u32 txsr; member
/u-boot/board/phytec/pcm052/
A Dpcm052.c127 .txsr = 506, in dram_init()
182 .txsr = 512, in dram_init()
/u-boot/doc/device-tree-bindings/memory-controllers/
A Dst,stm32-fmc.txt20 txsr
/u-boot/arch/arm/include/asm/arch-omap3/
A Dmem.h82 #define ACTIM_CTRLB(twtr, tcke, txp, txsr) \ argument
86 ACTIM_CTRLB_TXSR(txsr)
/u-boot/drivers/net/
A Dzynq_gem.c141 u32 txsr; /* 0x14 - TX Status reg */ member
373 writel(0, &regs->txsr); in zynq_gem_init()
553 return wait_for_bit_le32(&regs->txsr, ZYNQ_GEM_TSR_DONE, in zynq_gem_send()
/u-boot/arch/arm/mach-imx/mx6/
A Dddr.c1048 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr; in mx6_lpddr2_cfg() local
1073 txsr = DIV_ROUND_UP(140000, clkper) - 1; in mx6_lpddr2_cfg()
1077 txsr = DIV_ROUND_UP(220000, clkper) - 1; in mx6_lpddr2_cfg()
1132 debug("txsr=%d\n", txsr); in mx6_lpddr2_cfg()
1188 mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) | in mx6_lpddr2_cfg()
/u-boot/arch/arm/mach-imx/
A Dddrmc-vf610.c160 DDRMC_CR31_TXSR(timings->txsr), &ddrmr->cr[31]); in ddrmc_ctrl_init_ddr3()
/u-boot/board/freescale/vf610twr/
A Dvf610twr.c121 .txsr = 468, in dram_init()
/u-boot/board/toradex/colibri_vf/
A Dcolibri_vf.c126 .txsr = 506, /* changed to conform to JEDEC in dram_init()

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