Searched refs:update_value (Results 1 – 3 of 3) sorted by relevance
| /u-boot/drivers/ddr/altera/ |
| A D | sdram_agilex.c | 75 u32 update_value; in sdram_mmr_init_full() local
77 update_value = hmc_readl(plat, NIOSRESERVED0); in sdram_mmr_init_full()
78 update_value = (update_value & 0xFF) >> 5; in sdram_mmr_init_full()
81 update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4); in sdram_mmr_init_full()
82 hmc_ecc_writel(plat, update_value, DDRIOCTRL); in sdram_mmr_init_full()
|
| A D | sdram_s10.c | 76 u32 update_value, io48_value, ddrioctl; in sdram_mmr_init_full() local
189 update_value = hmc_readl(plat, NIOSRESERVED0); in sdram_mmr_init_full()
190 hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL); in sdram_mmr_init_full()
203 update_value = match_ddr_conf(io48_value); in sdram_mmr_init_full()
204 if (update_value) in sdram_mmr_init_full()
205 ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF); in sdram_mmr_init_full()
221 update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) + in sdram_mmr_init_full()
234 (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) | in sdram_mmr_init_full()
|
| A D | sdram_arria10.c | 253 u32 update_value, io48_value; in sdram_mmr_init() local
280 update_value = readl(&socfpga_io48_mmr_base->niosreserve0); in sdram_mmr_init()
281 writel(((update_value & 0xFF) >> 5), in sdram_mmr_init()
304 update_value = match_ddr_conf(io48_value); in sdram_mmr_init()
305 if (update_value) in sdram_mmr_init()
306 writel(update_value, in sdram_mmr_init()
365 update_value = (caltim2_cfg_rd_to_pch + caltim4_cfg_pch_to_valid + in sdram_mmr_init()
378 (update_value << in sdram_mmr_init()
|
Completed in 12 milliseconds