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Searched refs:writeq (Results 1 – 25 of 37) sorted by relevance

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/u-boot/drivers/net/octeontx/
A Dxcv.c33 writeq(reset.u, XCVX_BASE + XCVX_RESET(0)); in xcv_init_hw()
38 writeq(reset.u, XCVX_BASE + XCVX_RESET(0)); in xcv_init_hw()
48 writeq(xcv_dll_ctl.u, XCVX_BASE + XCVX_DLL_CTL(0)); in xcv_init_hw()
53 writeq(reset.u, XCVX_BASE + XCVX_RESET(0)); in xcv_init_hw()
64 writeq(reset.u, XCVX_BASE + XCVX_RESET(0)); in xcv_init_hw()
69 writeq(reset.u, XCVX_BASE + XCVX_RESET(0)); in xcv_init_hw()
94 writeq(xcv_ctl.u, XCVX_BASE + XCVX_CTL(0)); in xcv_setup_link()
105 writeq(reset.u, XCVX_BASE + XCVX_RESET(0)); in xcv_setup_link()
111 writeq(reset.u, XCVX_BASE + XCVX_RESET(0)); in xcv_setup_link()
115 writeq(xcv_crd_ret.u, XCVX_BASE + XCVX_BATCH_CRD_RET(0)); in xcv_setup_link()
[all …]
A Dsmi.c109 writeq(smix_clk.u, priv->baseaddr + SMI_X_CLK); in octeontx_smi_setmode()
125 writeq(smix_wr_dat.u, priv->baseaddr + SMI_X_WR_DAT); in octeontx_c45_addr()
132 writeq(smix_cmd.u, priv->baseaddr + SMI_X_CMD); in octeontx_c45_addr()
178 writeq(smix_cmd.u, priv->baseaddr + SMI_X_CMD); in octeontx_phy_read()
217 writeq(smix_wr_dat.u, priv->baseaddr + SMI_X_WR_DAT); in octeontx_phy_write()
230 writeq(smix_cmd.u, priv->baseaddr + SMI_X_CMD); in octeontx_phy_write()
250 writeq(smi_en.u, priv->baseaddr + SMI_X_EN); in octeontx_smi_reset()
253 writeq(smi_en.u, priv->baseaddr + SMI_X_EN); in octeontx_smi_reset()
A Dnic_main.c43 writeq(val, nic->reg_base + offset); in nic_reg_write()
69 writeq(msg[0], mbx_addr); in nic_send_msg_to_vf()
70 writeq(msg[1], mbx_addr + 8); in nic_send_msg_to_vf()
72 writeq(msg[1], mbx_addr + 8); in nic_send_msg_to_vf()
73 writeq(msg[0], mbx_addr); in nic_send_msg_to_vf()
A Dbgx.c86 writeq(val, (void *)addr); in bgx_reg_write()
95 writeq(val | bgx_reg_read(bgx, lmac, offset), (void *)addr); in bgx_reg_modify()
228 writeq(dmac, (void *)addr); in bgx_flush_dmac_addrs()
611 writeq(rctl, GSER_BR_RXX_CTL(qlm, l)); in __rx_equalization()
617 writeq(reer, GSER_BR_RXX_EER(qlm, l)); in __rx_equalization()
633 writeq(rctl, GSER_BR_RXX_CTL(qlm, l)); in __rx_equalization()
/u-boot/drivers/spi/
A Docteon_spi.c159 writeq(mpi_cfg, base + MPI_CFG); in octeon_spi_claim_bus()
189 writeq(mpi_cfg, base + MPI_CFG); in octeon_spi_release_bus()
219 writeq(mpi_cfg, base + MPI_CFG); in octeon_spi_xfer()
235 writeq(wide_dat, base + MPI_WIDE_DAT); in octeon_spi_xfer()
242 writeq(mpi_tx, base + MPI_TX); in octeon_spi_xfer()
263 writeq(*tx_data++, base + MPI_DAT(i)); in octeon_spi_xfer()
271 writeq(mpi_tx, base + MPI_TX); in octeon_spi_xfer()
322 writeq(mpi_cfg, base + MPI_CFG); in octeontx2_spi_xfer()
347 writeq(mpi_xmit, base + MPI_XMIT); in octeontx2_spi_xfer()
378 writeq(wide_dat, base + MPI_WIDE_BUF(i)); in octeontx2_spi_xfer()
[all …]
/u-boot/drivers/watchdog/
A Docteontx_wdt.c57 writeq(val, priv->reg + CORE0_WDOG_OFFSET); in octeontx_wdt_start()
66 writeq(0, priv->reg + CORE0_WDOG_OFFSET); in octeontx_wdt_stop()
85 writeq(~0ULL, priv->reg + CORE0_POKE_OFFSET); in octeontx_wdt_reset()
/u-boot/arch/arm/lib/
A Dgic-v3-its.c151 writeq(val, (uintptr_t)(priv.gicr_base + GICR_PROPBASER)); in gic_lpi_tables_init()
158 writeq(val, in gic_lpi_tables_init()
173 writeq(val, (uintptr_t)(pend_base + offset)); in gic_lpi_tables_init()
179 writeq(val, (uintptr_t)(pend_base + offset)); in gic_lpi_tables_init()
/u-boot/board/phytium/durian/
A Ddurian.c89 writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE); in __asm_flush_l3_dcache()
97 writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE); in __asm_flush_l3_dcache()
/u-boot/drivers/mtd/nand/raw/
A Docteontx_bch.c88 writeq(1, bch->reg_base + BCH_CTL); in bch_reset()
94 writeq(~0ull, bch->reg_base + BCH_ERR_INT_ENA_W1C); in bch_disable()
95 writeq(~0ull, bch->reg_base + BCH_ERR_INT); in bch_disable()
380 writeq(cbuf.u, vf->reg_base + BCH_VQX_CMD_BUF(0)); in octeontx_pci_bchvf_probe()
382 writeq(ctl.u, vf->reg_base + BCH_VQX_CTL(0)); in octeontx_pci_bchvf_probe()
384 writeq(octeontx_bch_q[QID_BCH].base_paddr, in octeontx_pci_bchvf_probe()
A Docteontx_bch.h117 writeq(num_words, vf->reg_base + BCH_VQX_DOORBELL(0)); in octeontx_bch_write_doorbell()
A Docteontx_nand.c643 writeq(cmd->val[0], tn->base + NDF_CMD); in ndf_submit()
661 writeq(cmd->val[0], tn->base + NDF_CMD); in ndf_submit()
662 writeq(cmd->val[1], tn->base + NDF_CMD); in ndf_submit()
967 writeq(1, tn->base + NDF_DRBELL); in ndf_build_post_cmd()
980 writeq(bus_addr, tn->base + NDF_DMA_ADR); in ndf_setup_dma()
981 writeq(dma_cfg, tn->base + NDF_DMA_CFG); in ndf_setup_dma()
2044 writeq(ndf_misc, tn->base + NDF_MISC); in octeontx_nfc_init()
2053 writeq(ndf_misc, tn->base + NDF_MISC); in octeontx_nfc_init()
2160 writeq(ndf_misc, tn->base + NDF_MISC); in octeontx_pci_nand_disable()
2162 writeq(ndf_misc, tn->base + NDF_MISC); in octeontx_pci_nand_disable()
[all …]
/u-boot/drivers/i2c/
A Docteon_i2c.c262 writeq(val, base + TWSI_SW_TWSI); in twsi_write_sw()
286 writeq(val, base + TWSI_SW_TWSI); in twsi_read_sw()
520 writeq(0, base + TWSI_INT); in twsi_unblock()
522 writeq(TWSI_INT_SCL_OVR, base + TWSI_INT); in twsi_unblock()
525 writeq(TWSI_INT_SCL_OVR | TWSI_INT_SDA_OVR, base + TWSI_INT); in twsi_unblock()
527 writeq(TWSI_INT_SDA_OVR, base + TWSI_INT); in twsi_unblock()
529 writeq(0, base + TWSI_INT); in twsi_unblock()
745 writeq(val, twsi->base + TWSI_SW_TWSI); in octeon_i2c_set_bus_speed()
/u-boot/drivers/net/octeontx2/
A Dlmt.h33 writeq(0, nix->lmt_base + LMT_LF_LMTCANCEL()); in lmt_cancel()
A Dcgx.c90 writeq(dmac_cam0.u, reg_addr); in cgx_lmac_mac_filter_clear()
99 writeq(dmac_ctl0.u, reg_addr); in cgx_lmac_mac_filter_clear()
121 writeq(dmac_cam0.u, reg_addr); in cgx_lmac_mac_filter_setup()
129 writeq(dmac_ctl0.u, reg_addr); in cgx_lmac_mac_filter_setup()
A Dnix.h267 writeq(val, nix_af->nix_af_base + offset); in nix_af_reg_write()
284 writeq(val, nix->nix_base + offset); in nix_pf_reg_write()
301 writeq(val, npa_af->npa_af_base + offset); in npa_af_reg_write()
318 writeq(val, nix_af->npc_af_base + offset); in npc_af_reg_write()
A Dcgx.h71 writeq(val, cgx->reg_base + CMR_SHIFT(lmac) + offset); in cgx_write()
/u-boot/drivers/sysreset/
A Dsysreset_octeon.c22 writeq(1, data->base + RST_SOFT_RST); in octeon_sysreset_request()
/u-boot/arch/arm/mach-socfpga/
A Dspl_agilex.c67 writeq(0, CPU_RELEASE_ADDR); in board_init_f()
A Dspl_s10.c69 writeq(0, CPU_RELEASE_ADDR); in board_init_f()
/u-boot/include/linux/
A Dio.h54 writeq(value, addr); in iowrite64()
/u-boot/include/fsl-mc/
A Dfsl_mc_cmd.h129 writeq(cmd->params[i], &portal->params[i]); in mc_write_command()
132 writeq(cmd->header, &portal->header); in mc_write_command()
/u-boot/drivers/gpio/
A Docteon_gpio.c100 writeq(GPIO_BIT(offset), gpio->base + gpio->data->reg_offs + in octeon_gpio_dir_output()
128 writeq(GPIO_BIT(offset), gpio->base + gpio->data->reg_offs + in octeon_gpio_set_value()
/u-boot/arch/mips/include/asm/
A Dio.h369 #define writeq_relaxed writeq in BUILDIO_MEM()
393 #define writeq writeq in BUILDIO_MEM() macro
/u-boot/drivers/core/
A Dregmap.c479 #if defined(out_le64) && defined(out_be64) && defined(writeq)
485 writeq(*val, addr); in __write_64()
528 #if defined(out_le64) && defined(out_be64) && defined(writeq) in regmap_raw_write_range()
/u-boot/arch/x86/include/asm/
A Dio.h72 #define writeq(b, addr) (*(volatile u64 *)(addr) = (b)) macro
76 #define __raw_writeq writeq

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