Home
last modified time | relevance | path

Searched refs:MASK_INSR (Results 1 – 22 of 22) sorted by relevance

/xen/xen/arch/x86/hvm/
A Dvmsi.c259 *pval = MASK_INSR(msi_desc->msi_attrib.guest_masked, in msixtbl_read()
262 *pval |= (u64)MASK_INSR(msi_desc->msi_attrib.guest_masked, in msixtbl_read()
646 return MASK_INSR(MASK_EXTR(addr, MSI_ADDR_DEST_ID_MASK), in msi_gflags()
648 MASK_INSR(MASK_EXTR(addr, MSI_ADDR_REDIRECTION_MASK), in msi_gflags()
650 MASK_INSR(MASK_EXTR(addr, MSI_ADDR_DESTMODE_MASK), in msi_gflags()
652 MASK_INSR(MASK_EXTR(data, MSI_DATA_DELIVERY_MODE_MASK), in msi_gflags()
654 MASK_INSR(MASK_EXTR(data, MSI_DATA_TRIGGER_MASK), in msi_gflags()
A Dmtrr.c178 MASK_INSR(mtrr_state.fixed_enabled, in hvm_vcpu_cacheattr_init()
180 MASK_INSR(mtrr_state.enabled, MTRRdefType_E)); in hvm_vcpu_cacheattr_init()
696 MASK_INSR(mtrr_state->fixed_enabled, in hvm_save_mtrr_msr()
698 MASK_INSR(mtrr_state->enabled, MTRRdefType_E), in hvm_save_mtrr_msr()
A Dhpet.c47 #define HPET_TN_INT_ROUTE_CAP_VAL MASK_INSR(0x00f00000, HPET_TN_INT_ROUTE_CAP)
346 MASK_INSR(find_first_set_bit(timer_int_route_cap(h, tn)), in timer_sanitize_int_route()
A Dhvm.c3518 MASK_INSR(v->arch.hvm.mtrr.enabled, MTRRdefType_E) | in hvm_msr_read_intercept()
3519 MASK_INSR(v->arch.hvm.mtrr.fixed_enabled, in hvm_msr_read_intercept()
/xen/xen/include/asm-x86/guest/
A Dhyperv-hcall.h81 control |= MASK_INSR(rep_comp, HV_HYPERCALL_REP_START_MASK); in hv_do_rep_hypercall()
/xen/xen/drivers/passthrough/amd/
A Diommu_intr.c492 val |= MASK_INSR(entry.ptr32->flds.int_type, in amd_iommu_read_ioapic_from_ire()
494 val |= MASK_INSR(iommu->ctrl.ga_en in amd_iommu_read_ioapic_from_ire()
688 msg->data |= MASK_INSR(entry.ptr32->flds.int_type, in amd_iommu_read_msi_from_ire()
692 msg->data |= MASK_INSR(entry.ptr128->full.vector, in amd_iommu_read_msi_from_ire()
698 msg->data |= MASK_INSR(entry.ptr32->flds.vector, in amd_iommu_read_msi_from_ire()
/xen/xen/drivers/vpci/
A Dmsi.c30 return MASK_INSR(fls(pdev->msi_maxvec) - 1, PCI_MSI_FLAGS_QMASK) | in control_read()
31 MASK_INSR(fls(msi->vectors) - 1, PCI_MSI_FLAGS_QSIZE) | in control_read()
/xen/xen/arch/x86/hvm/vmx/
A Dvmx.c134 (x2apic_enabled ? dest : MASK_INSR(dest, PI_xAPIC_NDST_MASK))); in vmx_vcpu_block()
155 x2apic_enabled ? dest : MASK_INSR(dest, PI_xAPIC_NDST_MASK)); in vmx_pi_switch_to()
1712 MASK_INSR(type, INTR_INFO_INTR_TYPE_MASK) | in __vmx_inject_exception()
1713 MASK_INSR(trap, INTR_INFO_VECTOR_MASK); in __vmx_inject_exception()
1740 MASK_INSR(trap, INTR_INFO_VECTOR_MASK), in vmx_inject_extint()
1759 MASK_INSR(X86_EVENTTYPE_NMI, INTR_INFO_INTR_TYPE_MASK) | in vmx_inject_nmi()
1760 MASK_INSR(TRAP_nmi, INTR_INFO_VECTOR_MASK), in vmx_inject_nmi()
1842 MASK_INSR(_event.type, INTR_INFO_INTR_TYPE_MASK) | in vmx_inject_event()
1843 MASK_INSR(_event.vector, INTR_INFO_VECTOR_MASK), in vmx_inject_event()
3604 MASK_INSR(X86_EVENTTYPE_NMI, INTR_INFO_INTR_TYPE_MASK)) ) in vmx_idtv_reinject()
[all …]
A Dvvmx.c2453 u32 valid_mask = MASK_INSR(X86_EVENTTYPE_HW_EXCEPTION, in nvmx_n2_vmexit_handler()
/xen/xen/arch/x86/cpu/mtrr/
A Dgeneric.c424 MASK_INSR(mtrr_state.enabled, MTRRdefType_E) | in set_mtrr_state()
425 MASK_INSR(mtrr_state.fixed_enabled, MTRRdefType_FE); in set_mtrr_state()
/xen/xen/include/xen/
A Dlib.h10 #define MASK_INSR(v, m) (((v) * ((m) & -(m))) & (m)) macro
/xen/tools/tests/x86_emulator/
A Dx86-emulate.h49 #define MASK_INSR(v, m) (((v) * ((m) & -(m))) & (m)) macro
/xen/xen/arch/x86/pv/
A Dgrant_table.c41 pte_flags |= MASK_INSR((grant_flags >> _GNTMAP_guest_avail0), _PAGE_AVAIL); in grant_to_pte_flags()
/xen/xen/arch/x86/mm/shadow/
A Dtypes.h326 | MASK_INSR(gfn_x(gfn), SH_L1E_MMIO_GFN_MASK) in sh_l1e_mmio()
/xen/xen/arch/x86/x86_emulate/
A Dx86_emulate.h633 MASK_INSR((ext), X86EMUL_OPC_EXT_MASK))
A Dx86_emulate.c2698 ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); in x86_decode_twobyte()
2717 ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); in x86_decode_twobyte()
2721 ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); in x86_decode_twobyte()
2746 ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); in x86_decode_twobyte()
2783 ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); in x86_decode_twobyte()
2791 ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); in x86_decode_twobyte()
2833 ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); in x86_decode_0f38()
2885 ctxt->opcode |= MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); in x86_decode_0f3a()
3021 opcode = b | MASK_INSR(0x0f, X86EMUL_OPC_EXT_MASK); in x86_decode()
3027 opcode = b | MASK_INSR(0x0f38, X86EMUL_OPC_EXT_MASK); in x86_decode()
[all …]
/xen/xen/include/asm-x86/
A Ddomain.h547 #define IOPL(val) MASK_INSR(val, X86_EFLAGS_IOPL)
/xen/tools/libxl/
A Dlibxl_arm.c1005 val = MASK_INSR(HVM_PARAM_CALLBACK_TYPE_PPI, in libxl__arch_domain_init_hw_description()
1008 val |= MASK_INSR(HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_LOW_LEVEL, in libxl__arch_domain_init_hw_description()
A Dlibxl_internal.h141 #define MASK_INSR(v, m) (((v) * ((m) & -(m))) & (m)) macro
/xen/xen/arch/x86/
A Dphysdev.c415 curr->arch.pv.iopl = MASK_INSR(set_iopl.iopl, X86_EFLAGS_IOPL); in do_physdev_op()
A Dio_apic.c579 data |= MASK_INSR(desc->arch.vector, IO_APIC_REDIR_VECTOR_MASK); in set_ioapic_affinity_irq()
/xen/xen/arch/arm/
A Ddomain_build.c2300 val = MASK_INSR(HVM_PARAM_CALLBACK_TYPE_PPI, in evtchn_allocate()
2303 val |= MASK_INSR(HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_LOW_LEVEL, in evtchn_allocate()

Completed in 78 milliseconds