Searched refs:MSR_IA32_MTRR_PHYSBASE (Results 1 – 6 of 6) sorted by relevance
| /xen/xen/arch/x86/cpu/mtrr/ |
| A D | generic.c | 34 rdmsrl(MSR_IA32_MTRR_PHYSBASE(index), vr->base); in get_mtrr_var_range()
326 rdmsrl(MSR_IA32_MTRR_PHYSBASE(reg), _base); in generic_get_mtrr()
364 rdmsrl(MSR_IA32_MTRR_PHYSBASE(index), msr_content); in set_mtrr_var_ranges()
376 mtrr_wrmsr(MSR_IA32_MTRR_PHYSBASE(index), vr->base); in set_mtrr_var_ranges()
561 mtrr_wrmsr(MSR_IA32_MTRR_PHYSBASE(reg), vr->base); in generic_set_mtrr()
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| /xen/xen/include/asm-x86/ |
| A D | mtrr.h | 44 MSR_IA32_MTRR_PHYSBASE(0)) / 2)
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| A D | msr-index.h | 236 #define MSR_IA32_MTRR_PHYSBASE(n) (0x00000200 + 2 * (n)) macro
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| /xen/xen/arch/x86/hvm/ |
| A D | mtrr.c | 170 mtrr_var_range_msr_set(d, m, MSR_IA32_MTRR_PHYSBASE(i), in hvm_vcpu_cacheattr_init()
457 index = msr - MSR_IA32_MTRR_PHYSBASE(0); in mtrr_var_range_msr_set()
767 MSR_IA32_MTRR_PHYSBASE(i), in hvm_load_mtrr_msr()
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| A D | hvm.c | 3542 case MSR_IA32_MTRR_PHYSBASE(0)...MSR_IA32_MTRR_PHYSMASK(MTRR_VCNT_MAX - 1): in hvm_msr_read_intercept()
3545 index = msr - MSR_IA32_MTRR_PHYSBASE(0); in hvm_msr_read_intercept()
3685 case MSR_IA32_MTRR_PHYSBASE(0)...MSR_IA32_MTRR_PHYSMASK(MTRR_VCNT_MAX - 1): in hvm_msr_write_intercept()
3688 index = msr - MSR_IA32_MTRR_PHYSBASE(0); in hvm_msr_write_intercept()
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| /xen/xen/arch/x86/ |
| A D | e820.c | 471 rdmsrl(MSR_IA32_MTRR_PHYSBASE(i), base); in mtrr_top_of_ram()
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