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/linux/Documentation/kbuild/
A DKconfig.recursion-issue-0113 # * What values are possible for CORE?
15 # CORE_BELL_A_ADVANCED selects CORE, which means that it influences the values
16 # that are possible for CORE. So for example if CORE_BELL_A_ADVANCED is 'y',
17 # CORE must be 'y' too.
27 # CORE_BELL_A depends on CORE, so CORE influences CORE_BELL_A.
31 # regarding possible values of CORE itself again. Answering the original
32 # question of what are the possible values of CORE would make the kconfig
43 # CORE also consist of a solution to this recursive problem.
47 config CORE config
52 depends on CORE
[all …]
A DKconfig.recursion-issue-0225 # have. Let's assume we have some CORE functionality, then the kernel has a
32 # with CORE, one uses "depends on" while the other uses "select". Another
38 # To fix this the "depends on CORE" must be changed to "select CORE", or the
39 # "select CORE" must be changed to "depends on CORE".
49 config CORE config
54 depends on CORE
63 select CORE
/linux/drivers/net/wireless/mediatek/mt76/mt76x0/
A Dinitvals_init.h87 { MT_BBP(CORE, 1), 0x00000002 },
88 { MT_BBP(CORE, 4), 0x00000000 },
89 { MT_BBP(CORE, 24), 0x00000000 },
90 { MT_BBP(CORE, 32), 0x4003000a },
91 { MT_BBP(CORE, 42), 0x00000000 },
92 { MT_BBP(CORE, 44), 0x00000000 },
A Dphy.c191 val = mt76_rr(dev, MT_BBP(CORE, 0)); in mt76x0_phy_wait_bbp_ready()
516 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
521 mt76_wr(dev, MT_BBP(CORE, 34), val); in mt76x0_phy_tssi_dc_calibrate()
534 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x0_phy_tssi_dc_calibrate()
550 mt76_wr(dev, MT_BBP(CORE, 34), val); in mt76x0_phy_tssi_adc_calibrate()
562 mt76_wr(dev, MT_BBP(CORE, 34), 0x80041); in mt76x0_phy_tssi_adc_calibrate()
566 mt76_wr(dev, MT_BBP(CORE, 34), 0x80042); in mt76x0_phy_tssi_adc_calibrate()
570 mt76_wr(dev, MT_BBP(CORE, 34), 0x80043); in mt76x0_phy_tssi_adc_calibrate()
746 data = mt76_rr(dev, MT_BBP(CORE, 1)); in mt76x0_phy_get_delta_power()
996 mt76_set(dev, MT_BBP(CORE, 1), 0x20); in mt76x0_phy_set_channel()
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt76x2/
A Dmac.c37 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2_mac_stop()
38 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2_mac_stop()
40 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2_mac_stop()
41 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2_mac_stop()
A Dpci_phy.c83 mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 2); in mt76x2_phy_set_antenna()
85 mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 4); in mt76x2_phy_set_antenna()
94 mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 1); in mt76x2_phy_set_antenna()
96 mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 1); in mt76x2_phy_set_antenna()
107 mt76_clear(dev, MT_BBP(CORE, 32), GENMASK(21, 20)); in mt76x2_phy_set_antenna()
108 mt76_clear(dev, MT_BBP(CORE, 33), GENMASK(12, 9)); in mt76x2_phy_set_antenna()
A Dusb_mac.c143 mt76_set(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
144 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1)); in mt76x2u_mac_stop()
146 mt76_set(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
147 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0)); in mt76x2u_mac_stop()
A Dphy.c218 if (mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4)) in mt76x2_phy_tssi_compensate()
/linux/Documentation/devicetree/bindings/regulator/
A Dnvidia,tegra-regulators-coupling.txt11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
19 and CPU voltages shall be in a range of 300mV from each other and CORE
/linux/drivers/infiniband/hw/hfi1/
A Dchip_registers.h9 #define CORE 0x000000000000 macro
10 #define CCE (CORE + 0x000000000000)
11 #define ASIC (CORE + 0x000000400000)
12 #define MISC (CORE + 0x000000500000)
13 #define DC_TOP_CSRS (CORE + 0x000000600000)
14 #define CHIP_DEBUG (CORE + 0x000000700000)
15 #define RXE (CORE + 0x000001000000)
16 #define TXE (CORE + 0x000001800000)
/linux/drivers/cpufreq/
A Dimx-cpufreq-dt.c39 CORE, enumerator
73 clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk); in imx7ulp_target_intermediate()
/linux/arch/arm/boot/dts/
A Domap5-core-thermal.dtsi2 * Device Tree Source for OMAP543x SoC CORE thermal
/linux/arch/arm/mach-omap2/
A DKconfig212 access SDRAM during CORE DVFS, select Y here. This should boost
213 SDRAM performance at lower CORE OPPs. There are relatively few
A Dsleep34xx.S354 cmp r4, #0x0 @ Check if previous power state of CORE is OFF
374 cmp r2, #0x0 @ Check if previous power state of CORE is OFF
/linux/Documentation/devicetree/bindings/mfd/
A Dda9052-i2c.txt19 buck1 : regulator BUCK CORE
/linux/drivers/gpu/drm/nouveau/dispnv50/
A Dcrc907d.c32 u32 crc_args = NVDEF(NV907D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) | in crc907d_set_src()
A Dbase907c.c170 NVDEF(NV907C, SET_CSC_RED2RED, OWNER, CORE)); in base907c_csc_clr()
/linux/drivers/net/wireless/mediatek/mt76/
A Dmt76x02_phy.c143 mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val); in mt76x02_phy_set_bw()
/linux/Documentation/gpu/
A Dkomeda-kms.rst328 achieve this, split the komeda device into two layers: CORE and CHIP.
330 - CORE: for common features and capabilities handling.
333 CORE can access CHIP by three chip function structures:
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
A Dphy_n.c16314 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, in wlc_phy_workarounds_nphy_rev7()
16317 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, in wlc_phy_workarounds_nphy_rev7()
16320 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, in wlc_phy_workarounds_nphy_rev7()
16338 CORE, coreNum, in wlc_phy_workarounds_nphy_rev7()
16346 CORE, coreNum, in wlc_phy_workarounds_nphy_rev7()
16350 CORE, coreNum, in wlc_phy_workarounds_nphy_rev7()
16354 CORE, coreNum, in wlc_phy_workarounds_nphy_rev7()
16358 CORE, coreNum, in wlc_phy_workarounds_nphy_rev7()
16362 CORE, coreNum, in wlc_phy_workarounds_nphy_rev7()
16388 WRITE_RADIO_REG4(pi, RADIO_2057, CORE, in wlc_phy_workarounds_nphy_rev7()
[all …]
/linux/Documentation/arm/omap/
A Domap_pm.rst42 3. Set the maximum system DMA transfer start latency (CORE pwrdm)::
/linux/Documentation/RCU/
A DwhatisRCU.rst32 :ref:`2. WHAT IS RCU'S CORE API? <2_whatisRCU>`
34 :ref:`3. WHAT ARE SOME EXAMPLE USES OF CORE RCU API? <3_whatisRCU>`
133 2. WHAT IS RCU'S CORE API?
395 3. WHAT ARE SOME EXAMPLE USES OF CORE RCU API?
/linux/drivers/tty/serial/jsm/
A Djsm_tty.c396 jsm_dbg(CORE, &brd->pci_dev, in jsm_tty_init()
/linux/Documentation/driver-api/
A Dvfio-mediated-device.rst60 | MDEV CORE |
/linux/Documentation/admin-guide/
A Dras.rst283 Controller (MC) driver modules. On a given system, the CORE is loaded
284 and one MC driver will be loaded. Both the CORE and the MC driver (or
289 both the CORE's and the MC driver's versions.

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