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Searched refs:mmMP0_SMN_C2PMSG_67 (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
A Dpsp_v11_0_8.c179 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); in psp_v11_0_8_ring_get_wptr()
193 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); in psp_v11_0_8_ring_set_wptr()
A Dpsp_v10_0.c236 return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); in psp_v10_0_ring_get_wptr()
243 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); in psp_v10_0_ring_set_wptr()
A Dpsp_v3_1.c381 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); in psp_v3_1_ring_get_wptr()
396 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); in psp_v3_1_ring_set_wptr()
A Dpsp_v12_0.c398 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); in psp_v12_0_ring_get_wptr()
411 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); in psp_v12_0_ring_set_wptr()
A Dpsp_v11_0.c749 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); in psp_v11_0_ring_get_wptr()
763 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); in psp_v11_0_ring_set_wptr()
/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
A Dmp_10_0_offset.h98 #define mmMP0_SMN_C2PMSG_67 macro
A Dmp_12_0_0_offset.h98 #define mmMP0_SMN_C2PMSG_67 macro
A Dmp_11_0_offset.h98 #define mmMP0_SMN_C2PMSG_67 macro
A Dmp_11_0_8_offset.h98 #define mmMP0_SMN_C2PMSG_67 macro
A Dmp_9_0_offset.h98 #define mmMP0_SMN_C2PMSG_67 0x0083 macro
A Dmp_11_5_0_offset.h98 #define mmMP0_SMN_C2PMSG_67 macro

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