Searched refs:MCUCFG_BASE (Results 1 – 20 of 20) sorted by relevance
154 #define MCUCFG_CPUSYS0_SPARKVRETCNTRL (MCUCFG_BASE + 0x1c00)162 #define MCUCFG_CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1c30)163 #define MCUCFG_CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1c34)164 #define MCUCFG_CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1c38)165 #define MCUCFG_CPUSYS0_CPU3_SPMC_CTL (MCUCFG_BASE + 0x1c3c)171 #define MCUCFG_MP2_BASE (MCUCFG_BASE + 0x2000)185 #define MCUCFG_MP0_SPMC (MCUCFG_BASE + 0x788)
25 #define MCUCFG_BASE 0x0c530000 macro83 #define MT_L2_WRITE_ACCESS_RATE (MCUCFG_BASE + 0x604)84 #define MP0_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f0)85 #define MP1_CA7L_CACHE_CONFIG (MCUCFG_BASE + 0x7f4)86 #define EMI_WFIFO (MCUCFG_BASE + 0x0b5c)122 #define INT_POL_CTL0 (MCUCFG_BASE + 0xa80)123 #define SEC_POL_CTL_EN0 (MCUCFG_BASE + 0xa00)124 #define GIC_SYNC_DCM (MCUCFG_BASE + 0x758)
12 #define GIC_INT_MASK (MCUCFG_BASE + 0x5e8)
10 #define MP2_SYNC_DCM (MCUCFG_BASE + 0x2274)
168 static struct mt8183_mcucfg_regs *const mt8183_mcucfg = (void *)MCUCFG_BASE;
16 #define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000)17 #define CPCCFG_REG_BASE (MCUCFG_BASE + 0xA800)
19 #define MCUCFG_BASE (IO_PHYS + 0x200000) macro25 #define RGU_BASE (MCUCFG_BASE + 0x11000)28 #define TRNG_base (MCUCFG_BASE + 0x230000)
105 static struct mt6795_mcucfg_regs *const mt6795_mcucfg = (void *)MCUCFG_BASE;
86 #define CCI_CLK_CTRL (MCUCFG_BASE + 0x660)
22 #define MCU_BIU_BASE (MCUCFG_BASE)
13 #define MCUCFG_BASE (0x0C530000) macro
16 #define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
15 #define MCUCFG_BASE 0x0c530000 macro
26 #define MCUCFG_BASE (IO_PHYS + 0x200000) macro
104 static struct mt8173_mcucfg_regs *const mt8173_mcucfg = (void *)MCUCFG_BASE;
33 #define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
131 mmio_write_64(MCUCFG_BASE + 0x2200, 0x2092c820); in mp1_L2_desel_config()
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