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Searched refs:CLK_PCIE_P0_AXI_EN (Results 1 – 4 of 4) sorted by relevance

/u-boot/include/dt-bindings/clock/
A Dmt7629-clk.h186 #define CLK_PCIE_P0_AXI_EN 9 macro
A Dmt7622-clk.h245 #define CLK_PCIE_P0_AXI_EN 9 macro
/u-boot/arch/arm/dts/
A Dmt7622.dtsi232 <&pciesys CLK_PCIE_P0_AXI_EN>,
/u-boot/drivers/clk/mediatek/
A Dclk-mt7622.c481 GATE_PCIE(CLK_PCIE_P0_AXI_EN, CLK_TOP_HIF_SEL, 21),

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