Home
last modified time | relevance | path

Searched refs:REG_DRAM_TRAINING_CS_OFFS (Results 1 – 4 of 4) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_axp.h217 #define REG_DRAM_TRAINING_CS_OFFS 20 macro
A Dddr3_hw_training.c667 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_load_patterns()
670 reg = (0x1 << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_load_patterns()
A Dddr3_read_leveling.c75 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
197 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_read_leveling_sw()
A Dddr3_write_leveling.c88 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
511 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw_reg_dimm()

Completed in 10 milliseconds